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Tags: ALU

project.name
2 Stars     1526 Views
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JCU 500

JCU 500
Re-upload of the JCU 500, now with a proper IC setup, for extra franciness. You can see the original here: https://circuitverse.org/users/1577/projects/4133.
 Functions are as follows
  • 0 - A OR B
  • 1 - A AND B
  • 2 - A XOR B
  • 3 - A + B
  • 4 - A NOR B
  • 5 - A NAND B
  • 6 - A XNOR B
  • 7 - NOT (A + B)
  • 8 - A == B
  • 9 - A > B
  • A - A < B
  • B - 0
  • C - A != B
  • D - A <= B
  • E - A >= B
  • F - 255

project.name
1 Stars     883 Views
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Spaghett MK 1

Spaghett MK 1
An attempt at making a functional Computer

Tbf, I don't know if I made a "functional computer" as much as I made a mess.

project.name
6 Stars     534 Views
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JCU 500

JCU 500
After a bit of figuring out, I've now got the JCU500! The JCU500 is an ALU capable of performing every major function you would need it too, and can even perform comparisons, such as greater or less than. Also reused the old JCU100 in a "lite" form. Enjoy!

 Now all I need to do is make a computer for it...

project.name
2 Stars     401 Views
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JCU150

JCU150
The JCU150! Now bigger and better!

 Now it can compare stuff! Well, kinda. Still working on making a "greater than" and "less than" comparitor. If anyone knows how, please tell me!

project.name
3 Stars     422 Views
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JCU100

JCU100
A simple ALU device I made (My first actually). You can give it a whirl if you want.

 I'll try implementing it into another project at some point, hopefully a fully fledged computer or something like that.

project.name
3 Stars     524 Views
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JCU 501

JCU 501
New and improved JCU 501! The new JCU 501 contains two accumulators (one for each input), as well as capacity to handle it's own input stream.

Functions:
0 - A OR B
1 - A AND B
2 - A XOR B
3 - A + B
4 - A NOR B
5 - A NAND B
6 - A XNOR B
7 - !(A + B)
8 - A = B
9 - A > B
a - A < B
b - 0
c - A != B
d - A <= B
e - A >= B
f - 1

project.name
0 Stars     227 Views

ALU

ALU
ALU

project.name
0 Stars     265 Views
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Minimal ALU

Minimal ALU
ALU
An elegant ALU design with arithmetic, logical and bitwise operations. The design attempts to maintain modularity, allowing new operations to be added with ease.

project.name
0 Stars     154 Views

Micro_intro

Micro_intro
ALU

project.name
3 Stars     579 Views
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ALU Example

ALU Example
An example of an ALU for the CircuitVerse learning book:
https://learn.circuitverse.org/docs/alu.html

project.name
0 Stars     238 Views

ALU 32 Bits

ALU 32 Bits
ALU

project.name
46 Stars     5315 Views
Everything is working great in this build!  So I will be taking about a week break from this.
Well except single pixel drawing on GPU but more on that later.

I included a Hello World program and a screen clear test program running by default.
But I would love to see what programs people can come up with. So definitely fork this and make your own programs for it, and link them in the comments below!

Also I am working on adding more instructions for the cpu and the gpu, let me know what might be useful in the comments and definitely check my in progress updates below!

I am running into an issue with per pixel drawing giving a contention error which doesn't make sense as i have tested the chip. unless the rgb screen col and row pins are also outputs i don't get what is going on.

For now though i'm taking a break from that and working on implementing some more of the OPs.

Here is a list of instructions. I'll add descriptions soon.
Anything with a * before it is not implemented yet.
0 NOP [0]
1 JMP [1]
2 SETA [10]
3 SETB [11]
4 LDA [100]
5 LDB [101]
6 WRA [110]
7 WRB [111]

*8 IA [1000]
*9 IB [1001]
*10 DA [1010]
*11 DB [1011]
*12 SLA [1100]
*13 SLB [1101]
*14 SRA [1110]
*15 SRB [1111]

16 ADD [1 0000]
17 SUB [1 0001]
18 MUL [1 0010]
19 DIV [1 0011]

20 EQL [1 0100]
21 NEQL [1 0101]
22 GRT [1 0110]
23 LSS [1 0111]
24 GRQL [1 1000]
25 LEQL [1 1001]

26 SSP [1 1010]
27 PUSH [1 1011]
28 POP [1 1100]
29 LTS [1 1101]

*30 PROC [1 1110]
*31 EPROC [1 1111]

32 SAS [10 0000]

project.name
0 Stars     155 Views

simple ALU

simple ALU
ALU

project.name
1 Stars     269 Views
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My 4 Bit CPU, Not very standard so it might not actually be a CPU yet. **Made By Ben W.**


project.name
22 Stars     4085 Views
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User Image me

This is a CPU witch is capable of executing a lot of stuff in one clock cycle, and this CPU can shift left up to 7 times and shift right up to 7 times witch means that it is possible to  multiply and divide in one clock cycle if you program a table in the program memory. it has a 32 bit instruction width and a 8 bit address. it also has 

The ALU has the following operations:

  • ADD
  • SUBTRACT
  • SHIFT_LEFT (up to 7 times per cycle 3 bit)
  • SHIFT_RIGHT (up to 7 times per cycle 3 bit)
  • XOR
  • OR
  • NOT

This Was made by miles


project.name
0 Stars     104 Views

ALU multiplexer

ALU multiplexer

MULTIPLEXER ALU


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0 Stars     83 Views
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Pract 4

Pract 4

project.name
0 Stars     129 Views

32-bit ALU

32-bit ALU

project.name
0 Stars     108 Views

My Processor Design

My Processor Design

A basic ALU design for my personal projects.


project.name
0 Stars     64 Views
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ALU Basic Design

ALU Basic Design
ALU

project.name
0 Stars     67 Views
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ALU_ROrg2021

ALU_ROrg2021

Rechnerorganisation TU Berlin WS2021


project.name
0 Stars     223 Views

Femto-4v0.5 (Computer)

Femto-4v0.5 (Computer)

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Test code demonstrating basic functionality. First it uses most instructions to ensure they work, before showing the graphical capabilities of the computer.

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
15x15 pixel display

Will have:
An ALU capable of shift right and multiplying
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number register
Text outputs
Stack
Assembler (hopefully)
Save memory
Several pre-written carts to play with

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with. 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space, including many special registers like the program counter and the Memory Address Register. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there is only one cart). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc (subject to change). This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the least significant bit of the mode register is low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high too by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. Setting the second bit of the mode register will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. A value of 8 works consistently, though I have not toyed with values much higher. In future, additional execution options will likely be made available, the current planned ones being enabling falling edge execution as well as rising edge execution, to double the execution speed, updating graphics on both edges of the clock pulse, updating graphics every other clock pulse, updating graphics when the update graphics command is run, and disabling graphics. 

Graphics:
The Femto-4 is capable of driving a 15x15 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. Should a falling edge "fast execution" mode be added and work, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. The demonstration code uses two "sprites". The first "sprite" is the black background, and the second "sprite" is the red rectangle. The coordinate value of the red rectangle is incremented every frame, causing the animation. Had I had more storage I might have incremented the colour as well to show the colour capabilities of the Femto-4. Whilst driving a larger screen might be nice, given the limit in the number of instructions per second, it is unlikely that it could be well utilised, which is why I have chosen this screen size. A variation with larger screens may appear at some point, but this is a low priority for me. 

ALU:
The basic ALU (currently the only implemented bit of the ALU) was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift right, adding and subtracting. This is unlike my previous computer which had different chips for each operation it could do. Additional capability chips, such as multiplication and shifting right will be added later. 

General Registers:
This computer probably has more general registers than it should. What makes the 256 general registers unique is that they can be easily piped into the A and B operators when performing ALU operations. This allows ALU instructions to only have one operand, with the lower 8-bits being the register address of value A, and with the higher 8-bits being the register address of value B. 

Timing:
This computer is timed using a several standard delay chips. The pulse length running in to the computer is about 10k units long. This then runs into the pulse generator which pulses 32 unique lines with a 20k delay between them which can then be used to time when control lines pulse. This is bundled together into a 32-bit timing bus, which then uses bit selectors to select how much delay that pulse will have. This is why there are 32 sub-circuits which are effectively just bit specific bit selectors - they allow me to "compactly" build timing circuitry. In addition to the main delay of 20k between the chosen bits, I can add "on-delays" to further delay the control line, allowing me to ensure that control lines like the enable read line can be on before the register reads from them. "On-delays" were first constructed to ensure that the data out line did not have contention issues - it ensured that the previous address outputting data was disabled before the next address outputting data onto the line was enabled. They add 1k of delay on the rising edge, and less than 10 delay on the falling edge. This way I do not need to worry about "on-delays" increasing the delay of one command into the next. The "Fast Execution" loop gives a pulse of 300k, with a delay between pulses of around 600k. This ensures that the previous instruction will finish before the next instruction starts. I do not entirely understand how the timing system works, since the in my mind it should be producing contention issues, however proofing it against that breaks the system entirely. 

Other Notes:
You may note that I use 32b EEPROM banks instead of 16b ones. This choice was made to reduce the number of EEPROM banks required. Each half of the EEPROM's 32b output is treated as one address. Whilst this added a slight bit of additional complexity in writing, it halved the number of EEPROM banks required. This project was started when I realised that EEPROM banks could be that large, since a major sticking point in a previous attempt was the number of EEPROM banks required. (That attempt is private and completely dysfunctional. It also suffers from contention errors caused by incomplete splitters.)


project.name
0 Stars     153 Views

Femto-4v0.7 (Computer)

Femto-4v0.7 (Computer)

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Test "Hello World" code demonstrating text input and output functionality of the computer. Once the computer has outputted "Hello World! Type something!" it will shift in any input from the keyboard into the text output.

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
15x15 pixel display

Updates:
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number register
Text outputs

Will have:
An ALU capable of shift right and multiplying

Stack
Assembler (hopefully)
Save memory
Several pre-written carts to play with
Maybe separate GPU to help with graphics handling

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with. 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space, including many special registers like the program counter and the Memory Address Register. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there is only one cart). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc (subject to change). This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the least significant bit of the mode register is low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high too by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. A value of hex 10 (16) is the highest value I have found to work. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. This raises the max execution speed to 640 instructions per second. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for rising edge only (normal speed), 01 for duel edge (double speed), 10 for every other clock pulse (half speed), and 11 for when given the correct OP Code (controlled updates). The OP Code used for the graphics update is (01). The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics.

Graphics:
The Femto-4 is capable of driving a 15x15 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. Should a falling edge "fast execution" mode be added and work, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. The demonstration code uses two "sprites". The first "sprite" is the black background, and the second "sprite" is the red rectangle. The coordinate value of the red rectangle is incremented every frame, causing the animation. Had I had more storage I might have incremented the colour as well to show the colour capabilities of the Femto-4. Whilst driving a larger screen might be nice, given the limit in the number of instructions per second, it is unlikely that it could be well utilised, which is why I have chosen this screen size. A variation with larger screens may appear at some point, but this is a low priority for me. 

ALU:
The basic ALU (currently the only implemented bit of the ALU) was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift right, adding and subtracting. This is unlike my previous computer which had different chips for each operation it could do. Additional capability chips, such as multiplication and shifting right will be added later. 

General Registers:
This computer probably has more general registers than it should. What makes the 256 general registers unique is that they can be easily piped into the A and B operators when performing ALU operations. This allows ALU instructions to only have one operand, with the lower 8-bits being the register address of value A, and with the higher 8-bits being the register address of value B. 

Timing:
This computer is timed using a several standard delay chips. The pulse length running in to the computer is about 10k units long. This then runs into the pulse generator which pulses 32 unique lines with a 20k delay between them which can then be used to time when control lines pulse. This is bundled together into a 32-bit timing bus, which then uses bit selectors to select how much delay that pulse will have. This is why there are 32 sub-circuits which are effectively just bit specific bit selectors - they allow me to "compactly" build timing circuitry. In addition to the main delay of 20k between the chosen bits, I can add "on-delays" to further delay the control line, allowing me to ensure that control lines like the enable read line can be on before the register reads from them. "On-delays" were first constructed to ensure that the data out line did not have contention issues - it ensured that the previous address outputting data was disabled before the next address outputting data onto the line was enabled. They add 1k of delay on the rising edge, and less than 10 delay on the falling edge. This way I do not need to worry about "on-delays" increasing the delay of one command into the next. The "Fast Execution" loop gives a pulse of 300k, with a delay between pulses of around 600k. This ensures that the previous instruction will finish before the next instruction starts. I do not entirely understand how the timing system works, since the in my mind it should be producing contention issues, however proofing it against that breaks the system entirely. 

Other Notes:
You may note that I use 32b EEPROM banks instead of 16b ones. This choice was made to reduce the number of EEPROM banks required. Each half of the EEPROM's 32b output is treated as one address. Whilst this added a slight bit of additional complexity in writing, it halved the number of EEPROM banks required. This project was started when I realised that EEPROM banks could be that large, since a major sticking point in a previous attempt was the number of EEPROM banks required. (That attempt is private and completely dysfunctional. It also suffers from contention errors caused by incomplete splitters.) The memory wrappers allow external chips to interact with the main dat control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 


project.name
0 Stars     104 Views

Femto-4v0.7.1 (Computer)

Femto-4v0.7.1 (Computer)

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Outputs the twelve days of Christmas into the text output. 

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
15x15 pixel display

Updates:
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number register
Text outputs

Will have:
An ALU capable of shift right and multiplying

Stack
Assembler (hopefully)
Save memory
Several pre-written carts to play with
Maybe separate GPU to help with graphics handling

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with. 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space, including many special registers like the program counter and the Memory Address Register. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there is only one cart). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc (subject to change). This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the least significant bit of the mode register is low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high too by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. A value of hex 10 (16) is the highest value I have found to work. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. This raises the max execution speed to 640 instructions per second. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for rising edge only (normal speed), 01 for duel edge (double speed), 10 for every other clock pulse (half speed), and 11 for when given the correct OP Code (controlled updates). The OP Code used for the graphics update is (01). The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics.

Graphics:
The Femto-4 is capable of driving a 15x15 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. Should a falling edge "fast execution" mode be added and work, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. The demonstration code uses two "sprites". The first "sprite" is the black background, and the second "sprite" is the red rectangle. The coordinate value of the red rectangle is incremented every frame, causing the animation. Had I had more storage I might have incremented the colour as well to show the colour capabilities of the Femto-4. Whilst driving a larger screen might be nice, given the limit in the number of instructions per second, it is unlikely that it could be well utilised, which is why I have chosen this screen size. A variation with larger screens may appear at some point, but this is a low priority for me. 

ALU:
The basic ALU (currently the only implemented bit of the ALU) was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift right, adding and subtracting. This is unlike my previous computer which had different chips for each operation it could do. Additional capability chips, such as multiplication and shifting right will be added later. 

General Registers:
This computer probably has more general registers than it should. What makes the 256 general registers unique is that they can be easily piped into the A and B operators when performing ALU operations. This allows ALU instructions to only have one operand, with the lower 8-bits being the register address of value A, and with the higher 8-bits being the register address of value B. 

Timing:
This computer is timed using a several standard delay chips. The pulse length running in to the computer is about 10k units long. This then runs into the pulse generator which pulses 32 unique lines with a 20k delay between them which can then be used to time when control lines pulse. This is bundled together into a 32-bit timing bus, which then uses bit selectors to select how much delay that pulse will have. This is why there are 32 sub-circuits which are effectively just bit specific bit selectors - they allow me to "compactly" build timing circuitry. In addition to the main delay of 20k between the chosen bits, I can add "on-delays" to further delay the control line, allowing me to ensure that control lines like the enable read line can be on before the register reads from them. "On-delays" were first constructed to ensure that the data out line did not have contention issues - it ensured that the previous address outputting data was disabled before the next address outputting data onto the line was enabled. They add 1k of delay on the rising edge, and less than 10 delay on the falling edge. This way I do not need to worry about "on-delays" increasing the delay of one command into the next. The "Fast Execution" loop gives a pulse of 300k, with a delay between pulses of around 600k. This ensures that the previous instruction will finish before the next instruction starts. I do not entirely understand how the timing system works, since the in my mind it should be producing contention issues, however proofing it against that breaks the system entirely. 

Other Notes:
You may note that I use 32b EEPROM banks instead of 16b ones. This choice was made to reduce the number of EEPROM banks required. Each half of the EEPROM's 32b output is treated as one address. Whilst this added a slight bit of additional complexity in writing, it halved the number of EEPROM banks required. This project was started when I realised that EEPROM banks could be that large, since a major sticking point in a previous attempt was the number of EEPROM banks required. (That attempt is private and completely dysfunctional. It also suffers from contention errors caused by incomplete splitters.) The memory wrappers allow external chips to interact with the main dat control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 


project.name
0 Stars     105 Views

Femto-4 Basic ALU

Femto-4 Basic ALU
ALU

This is the Femto-4's basic ALU. This project is mostly a test project for testing the functionality of the Femto-4's basic ALU.

Femto-4 is found here:
https://circuitverse.org/users/4699/projects/femto-4v1-3-computer


project.name
1 Stars     285 Views

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Cart A: Flappy Bird
Cart B: Some Pixel Art
Cart C: Screensaver

Assembler:
https://repl.it/@Sanderokianstfe/Femto-4-Assembler#DeveloperGuide.txt

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks, allowing for a standard Cart to hold up to 512kx16b of data
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
16x16 pixel display
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number generator
Text outputs
An ALU capable of shift right, multiplying, dividing, and other specialised functions
Stack
Assembler (written in an external program)
Save memory
Two pre-written carts to play with
Fixed code controlled graphics updates
Made Bootloader clear TTY, Keyboard, and Controller Pushed
Fixed Register ALU instructions
Updated Cart A and Cart B to make use of the Register ALU instructions

Updates:
Another pre-written cart to play with
Updated the sprite-art cart to respond to the start button on both controllers. 

Will have:
More pre-written carts
Bug fixes

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note:
The Flappy Bird high score is mine. If you want to save your own scores permanently you will have to fork it. 

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with (and there are a lot of ALU processes). 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there are currently only two carts). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers, the, stack, inputs, outputs, and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high to by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0x0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. It is also paused by the OP Code 0x0001. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for falling edge only (normal speed), 01 for dual edge (double speed), 10 for every other clock pulse (half speed), and 11 for code controlled, where the 0x0001 OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. 

Graphics:
The Femto-4 is capable of driving a 16x16 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. When using dual-edge "Faster Execution", the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. 

ALU:
The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting. This is unlike my previous computer which had different chips for each operation it could do. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the Femto-4's graphics data. 

Conditional Jumps:
The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. 
The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. In theory a similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not.
The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing:
This computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. For more information see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction

Other Notes:
The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 






This is a secret to everybody, unless you found it. 


project.name
1 Stars     53 Views

ALU

ALU
ALU

ALU


project.name
0 Stars     115 Views

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Cart A: Flappy Bird
Cart B: Some Pixel Art

Assembler:
https://repl.it/@Sanderokianstfe/Femto-4-Assembler#DeveloperGuide.txt

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks, allowing for a standard Cart to hold up to 512kx16b of data
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
16x16 pixel display
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number generator
Text outputs
An ALU capable of shift right, multiplying, dividing, and other specialised functions
Stack
Assembler (written in an external program)
Save memory
One pre-written cart to play with

Updates:
Another pre-written cart
Fixed code controlled graphics updates
Made Bootloader clear TTY, Keyboard, and Controller Pushed
Fixed Register ALU instructions
Updated Cart A and Cart B to make use of the Register ALU instructions

Will have:
More pre-written carts
Bug fixes

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note:
The Flappy Bird high score is mine. If you want to save your own scores permanently you will have to fork it. 

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with (and there are a lot of ALU processes). 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there are currently only two carts). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers, the, stack, inputs, outputs, and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high to by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0x0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. It is also paused by the OP Code 0x0001. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for falling edge only (normal speed), 01 for dual edge (double speed), 10 for every other clock pulse (half speed), and 11 for code controlled, where the 0x0001 OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. 

Graphics:
The Femto-4 is capable of driving a 16x16 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. When using dual-edge "Faster Execution", the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. 

ALU:
The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting. This is unlike my previous computer which had different chips for each operation it could do. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the Femto-4's graphics data. 

Conditional Jumps:
The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. 
The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. In theory a similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not.
The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing:
This computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. For more information see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction

Other Notes:
The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 






This is a secret to everybody, unless you found it. 


project.name
57 Stars     94527 Views

A 16-bit computer/maybe console inspired thing, the Femto-4. This will be the main branch and backups will be forks from it. This project was started around November 2020.

Currently runs: 

  • Cart A: Flappy Bird 
  • Cart B: Some Pixel Art 
  • Cart C: Screensaver 
  • Cart D: Snake 
  • Cart E: Phemton Demonstrations 
  • Cart F: Competitive Snake 
  • Cart G: Tic Tac Toe 
  • Cart H: Connect 4 
  • Cart I: NIM
  • Cart J: Bad Apple
  • Bundle Cart: All carts in one 
  • Cart 2A: 32x32 Snake
  • Cart 2B: 32x32 Competitive Snake
  • Cart 2C: 32x32 Pixel Art
  • Cart 2D: 32x32 Bad Apple
  • Bundle Cart 2: All 32x32 carts in one 

Assembler: 

Compiler: 

The 256-Series: 

Full screen Notes:

For some reason, the Femto-4v2.6 only is having issues around caching previous subcircuits. Should you need to use something to unbind key entries from the full screen button, toggle the clock. Previous versions are completely unaffected. 

Cart Notes: 

Cart A: 

  • The first cart written for the Femto-4. 

Cart B: 

  • The sprites in the cart are: 
  • A: Femto-4 Logo. 
  • B: Madeline from Celeste. 
  • C: Madeline from Celeste (again). 
  • D: Part of you aka Badeline from Celeste. 
  • E: A strawberry from Celeste.
  • F: Standing Mario from Super Mario Bros. 
  • G: Jumping Mario from Super Mario Bros. 
  • H: Standing Mario from Super Mario Bros 3. 
  • I: Running Mario from Super Mario Bros 3. 
  • J: Sanderokian (my own character). 

Cart C: 

  • Enter anything into the keyboard to randomise the colours. 
  • Enter r into the keyboard to reset the colours. 

Cart D: 

  • WASD Pad is recommended. 
  • Game settings (enter the letter before starting the game to use the setting): 
  • e: toggle whether crashing into the edges results in a game over. 
  • The two modes (with/without edge collisions) have two separate high scores. 
  • w: change the snake's colour scheme to white. 
  • r: change the snake's colour scheme to red. 
  • y: change the snake's colour scheme to yellow. 
  • o: change the snake's colour scheme to orange. 
  • p: change the snake's colour scheme to purple. 
  • a: change the snake's colour scheme to aqua. 
  • g: change the snake's colour scheme to green. 
  • b: change the snake's colour scheme to blue. 
  • m: change the snake's colour scheme to magenta. 
  • 1: change the snake's colour scheme to pink. 
  • 2: change the snake's colour scheme to light blue. 
  • 3: change the snake's colour scheme to the challenge colour scheme with an invisible body. 
  • 0: randomise the snake's colour scheme. 

Cart E: 

  • The test codes in the cart are: 
  • 1: Hello World. 
  • 2: Single Operator Calculator. 
  • 3: Exponentiation Calculator. 
  • 4: Fibonacci Calculator. 
  • 5: Keyboard to TTY Test. 
  • 6: Keyboard to TTY LDI LID Test. 
  • 7: Keyboard to TTY LII Test. 
  • 8: Keyboard to TTY LIA Test. 

Cart F: 

  • WASD Pad is essentially required. 
  • Game settings (enter the letter before starting the game to use the setting): 
  • e: toggle whether crashing into the edges results in a game over. 
  • w: toggle whether the number of wins each player has is tracked. 
  • s: toggle whether the total score each player has scored is tracked. 
  • d: display the total wins and total scored. 
  • r: reset the tracked statistics. 

Cart G: 

  • The small light in the corner indicates which player's turn it is. 
  • When it is dimmed, it means that the computer is processing that player's turn. 
  • Game settings (enter the letter before starting the game to use the setting): 
  • w: toggle whether the number of wins each player has is tracked. 
  • s: toggle automatic start player swapping. d: display the wins each player has. 
  • r: reset the wins each player has. 

Cart H: 

  • The bar at the top indicates which player's turn it is. 
  • When it is dimmed, it means that the computer is processing that player's turn. 
  • Game settings (enter the letter before starting the game to use the setting): 
  • w: toggle whether the number of wins each player has is tracked. 
  • s: toggle automatic start player swapping. 
  • d: display the wins each player has. 
  • r: reset the wins each player has.

Cart I:

  • Game settings (enter the letter before starting the game to use the setting):
  • w: toggle whether the number of wins each player has is tracked. 
  • s: toggle automatic start player swapping. 
  • d: display the wins each player has. 
  • r: reset the wins each player has. 
  • i: display the game instructions. 
  • c: toggle the whether player 2 is played by the computer. 

Cart J:

  • Plays Bad Apple
  • There are no further controls

Cart 2A:

  • The options are the same as Cart D. 

Cart 2B:

  • The options are the same as Cart F. 

Cart 2C:

  • The sprites in the cart are: 
  • A: Femto-4 Logo. 
  • B: Sanderokian (my own character). 
  • C: Alstran (my own character). 

Cart 2D:

  • Plays Bad Apple on the larger screen
  • There are no further controls

Features: 

  • Immediate, direct, & indirect memory access. 
  • Jumps & conditional jumps. 
  • 16-bit address space. 
  • Switchable memory banks, allowing for a standard cart to hold up to 1MB of data. 
  • An ALU capable of logical operators, addition, subtraction, shift left, shift right, multiplying, dividing, & other specialised functions. 
  • Fast execution - can run more than one instruction per clock cycle. 
  • 16x16 pixel display with 32 sprites and 15-bit direct colour. 
  • 32x32 pixel display with 32 sprites which can have up to 18-bit direct colour. 
  • Two controllers, a keyboard mapping for the controllers, & a keyboard for text inputs. 
  • RNG, TTY, stack, & save memory. 
  • Von Neumann Architecture. 
  • Assembler & compiler (written in Python). 
  • Twelve pre-written carts to play with. 

Updates: 

v1.0: 

  • Finished the project and added Cart A. 

v1.1: 

  • Added Cart B, some Pixel Art. 
  • Fixed GRF, & AXR instructions. 
  • Made Bootloader clear TTY, Keyboard, & Controller Pushed. 
  • Updated Cart A & Cart B to make use of AXR instructions. 

v1.2: 

  • Added Cart C, a Screensaver. 
  • Updated Cart B to respond to the start button on both controllers. 

v1.3: 

  • Added Cart D, Snake. 
  • Moved to new project to fix issues around searching for projects branched from private projects. 
  • Removed unnecessary EEPROM banks and write lines from all carts. 
  • Made Reset clear WRAM and the General Registers. 

v1.4: 

  • Fixed Keyboard. 
  • Added a Bundle Cart that allows you to view all the carts without changing carts (you must reset the console to view another cart). 
  • Fixed bug in the standard bank design which wrote data to incorrect addresses. 
  • Fixed contention issue in Mult. 
  • Added Annotations to the In Debug. 

v1.5: 

  • Added Snake Player. 
  • Added Reset & Power labels to the relevant buttons. 

v2.0: 

  • Further optimisation to reduce lag/increase execution speed. 
  • Added more memory access options. 

v2.1: 

  • Further optimisation of the CU. 
  • Added a keyboard to controller mapping. 

v2.2: 

  • Continued optimisation and overhaul of the CU. 
  • Removed old CU & compare circuits. 
  • Added additional stack access instructions. 
  • Updated the debug versions with the changes, as well as fixing bugs in the debug versions. 
  • Designed a Logo for the Femto-4. 
  • Rewrote Cart C to allow the sprites to be viewed in any order, and added the logo to it. 

v2.3: 

  • Introducing Phemton Lite, the first version of the Femto-4's high level languages. 
  • Added a link to Phemton Lite's compiler. 
  • Added Cart E to demonstrate code written in Phemton Lite. 
  • Combined SpecialD & ROMD1, and removed SpecialD & ROMDB. 
  • Updated Snake code & Bundle code to match the new addresses. 
  • Added Cart F, a competitive version of Snake. 
  • Added an additional sprite into Cart B. 
  • Fixed issues with LII, LXA & LXP instructions. 

v2.4: 

  • Fixed alignment of the upper carts. 
  • Added Cart G & Cart H, Tic Tac Toe & Connect 4 written in Phemton Lite. 
  • Added progress lights to Cart G & Cart H. 
  • Reworked bundle cart to make the code shorter and more efficient for large numbers of carts. 
  • Made Cart G & Cart H faster. 
  • Reshuffled Cart E test codes and added 2 Cart E test codes, exponentiation & Fibonacci calculation. 
  • Added game options to Cart D, Cart F, Cart G, & Cart H. 
  • Updated Cart C to allow the colours to be randomised. 
  • Added optional colour schemes for Cart D. 
  • Fixed Snake Player. 
  • Remade the multiply and divide circuits to take advantage of the inbuilt adders. 
  • Removed old MultM and DivM circuits. 

v2.5: 

  • Further optimisation of the CU. 
  • Optimisation of the fast execution clocks for the computer, the graphics, & the WASD Pad. 
  • Fixed debug versions' issues with Phemton conditionals and added optimisations to the debug versions. 
  • Added 32x32 screen PPU. 
  • Added Cart 2A, Cart 2B, & Cart 2C, 32x32 versions of Snake, Competitive Snake, & Pixel Art. 
  • Added Cart I, NIM written in Phemton Lite. 

v2.6

  • Added the ability to directly write sprites to the PPU during execution.
  • Significantly optimised the CU by removing unnecessary subcircuits.
  • Introduced significant quantities of lazy evaluation to further improve performance.
  • Added Cart J, and Cart 2D, which both play Bad Apple.
  • The Femto-4 can now be added to the set of things that plays Bad Apple.

Future Updates: 

  • More pre-written carts. 
  • Bug fixes. 
  • Adding an optimiser to the compiler. 
  • Phemton Full. 
  • Phemton Plus. 

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note: The Flappy Bird high score and the Snake high score are mine. If you want to save your own scores permanently you will have to fork the project. 

The Femto-4

 Femto-4 Logo

General Architecture: The Femto-4 is a 16-bit, Von Neumann architecture computer with variable length instructions that are comprised of multiple 16-bit words. It has many features associated with CISCs, such as variable length instructions, and multicycle indirect loads, however operates like a RISC, with each instruction taking exactly 1 clock cycle. This was done to give the Femto-4 power whilst keeping its construction simple. First the OP code of the instruction is read, and then depending on the OP code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP code space is so empty that the data will likely be passed one at a time until the next valid instruction. Instructions are read from main memory, making this architecture a Von Neumann architecture as opposed to a Harvard architecture. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to most special registers during the instruction. OP codes and operands are all 16-bits. The large OP code size was chosen due to the high number of ALU instructions. There are approximately 500 interpretable OP codes that the computer can handle. 

Memory Mapping: The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 0b01, 0b10, or 0b11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 0x00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed WRAM chip that cannot be switched out, the bootloader, the PPU data, general registers, the stack, inputs, outputs, and a few special registers, such as the protect, mode, and flag registers. 

Fast Execution: Execution at the fastest clock speed (one pulse every 100ms, or 10Hz, which is defined as the clock changing state every 50ms, or at a rate of 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 0x00ca, the mode register, and address 0x00cb, the protect register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When bit 0 is set high, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping an inverter into itself, producing a loop that will pulse indefinitely until the looping line is stopped by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. Fast execution is always paused by a 0x0000 and 0x0001 OP Code. Bit 2 enables falling edge fast execution, which can be done with rising edge fast execution producing dual edge fast execution. Setting the third bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protect register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 0b00 for falling edge only (normal speed), 0b01 for dual edge (double speed), 0b10 for every other clock pulse (half speed), and 0b11 for code controlled, where the 0x0001OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics, reducing lag by prevent the graphics fast execution loop from running. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. By default, the Femto-4 executes with a protection value of 16, to allow the carts to run smoothly, however, depending on the instructions being used, that number can be raised to 64. 

Graphics (16x16): The Femto-4 is capable of driving a 16x16 15-bit direct colour screen. It has space for 32 sprites which are rectangles with an assigned colour. All the sprites are drawn to the screen whenever a graphics update occurs, depending on the graphics mode. When using dual-edge fast execution, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 sprites have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x coordinate 1 (4), x coordinate 2 (4), y coordinate 1 (4), y coordinate 2 (4). The second coordinates are offset up by 1, to allow the full screen to be drawn to, such that the dimensions of the rectangle are (x2 - x1) + 1 and (y2 - y1) + 1. The next 16 bits are the sprites colour, with the first 15 bits being used for 15-bit direct colour, and the last bit being used to enable or disable drawing the sprite. The last bit is important to ensure that blank sprites are not drawn to the screen. Since the screen is not wiped every time it is refreshed, the background must be a sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed (see how Snake works). The sprites are drawn in memory order, with the sprite with the largest address always being drawn last and therefore on top, of all other sprites. This is achieved by using the exact same system as fast execution, which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically decreases the simulation's stack usage. 

Graphics (32x32): The Femto-4 can also drive a 32x32 screen, with sprites able to be drawn through 3 different modes. The 32x32 screen PPU treats the addresses as one combined 32-bit value, with the value with the smaller address going first. The first 3 bits of the 32 bits define the mode. Only the values 1, 2, 3, correspond to actual sprites, whilst the rest are not drawn to the screen. Mode 1 splits the remaining 29-bit space as the following: unused (1), x coordinate (5), y coordinate (5), red (6), green (6), blue (6). Mode 2 splits the 29-bit space in the following way: x coordinate 1 (5), x coordinate 2 (5), y coordinate 1 (5), y coordinate 2 (5), red (3), green (3), blue (3). Mode 3 splits the 29-bit space in the following way: unused (3), x coordinate (5), y coordinate (5), red (5), green (5), blue (5), alpha/transparency (1). As with the 16x16 screen, Mode 2's second coordinates are offset by 1 resulting in rectangles having the dimensions of (x1 - x2) + 1 and (y1 - y2) + 1. Mode 3 is designed to allow the colours used in the 16x16 screen to be the same, making converting code between the two versions easier. The update mechanism is the same as 16x16 screen. 

ALU: The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting, reducing the number of circuits required, as well as the logic required to decide which instruction to use. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the computer's graphics data. 

Conditional Jumps: The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. A similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not. Bit testing is most useful for testing an input from both controllers, since it can cut out an additional instruction. The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing: The computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. These pulses can tell registers to write and what source to write from, enable the read and write lines, update the ALU, and update the stack Each instruction is separate by 600k of delay in fast execution. For more information on how delay works see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction

Keyboard Mapping: The Femto-4's keyboard controller mapping was created using a specialised chip. This chip used the fast execution loop to take 15 inputs from a keyboard and map the inputs to button presses on the controllers. Since the buttons are updated several times in a clock pulse, the keyboard controller cannot handle held buttons. The keyboard mapping is designed to work with both controllers, allowing two player games to be feasible on the computer. 

Assembly: The Femto-4 has an assembler that converts assembly written in a .txt into hex values in a .txt that can be copied and loaded into the EEPROM banks for storage. The assembler can handle symbol assignment, as well as assigning addresses in the code symbols to make handling jumps easier. For full details on the Femto-4's assembly language view the assembly developer guide. 

Phemton: Phemton is the Femto-4's high level language, with a compiler to compile it's code into Femto-4 assembly. Phemton handles variable memory assignment, basic array assignment, if, elif, else statments, while loops, for loops, and functions. Phemton Lite is the only compiler complete, and lacks an optimiser. Phemton Lite has the concept of local scope only when compiling. All uniquely identified variables are given a global address. This reduces the runtime load since the computer does not need to decide where the variables need to go during run time. Future planned additions include generated code optimisations and optimisers, Phemton Full, which has dynamic memory assignment, and Phemton Plus, which adds additional types for floats and longs. For more details view Phemton's developer guide. 

Other Notes: The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. This makes it easy to additional chips to the computer. All assembly and Phemton code can be found in the project for the Femto-4's assembler and compiler respectively. The save data cart must be located outside of the Femto-4 circuit to ensure that its contents are automatically saved. Sorry about all the copies of this computer clogging up the top of the search results. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 

This is a secret to everybody, unless you found it. 


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0 Stars     41 Views

ALU

ALU
ALU

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Basic ALU Design

Basic ALU Design

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Untitled

Untitled
ALU

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ALU

ALU
ALU

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0 Stars     115 Views
User:

74181 ALU xjnu

74181 ALU xjnu

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1 Stars     67 Views
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ALU

ALU

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0 Stars     18 Views

Basic ALU

Basic ALU
ALU

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0 Stars     21 Views

ALU

ALU
ALU

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0 Stars     96 Views
User:

Computer Systems Architecture

32-bit ALU, only with AND, OR, and ADDER/SUBTRACTOR.


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0 Stars     48 Views
User:

16 BIT ALU CIRCUIT

16 BIT ALU CIRCUIT

project.name
0 Stars     108 Views

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a branch to keep a functional version around. This project was started around November 2020.

Currently runs:
Cart A: Flappy Bird
Cart B: Some Pixel Art
Cart C: Screensaver
Cart D: Snake
Bundle Cart: All carts in one

Assembler:
https://repl.it/@Sanderokianstfe/Femto-4-Assembler#DeveloperGuide.txt

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks, allowing for a standard cart to hold up to 512kx16b of data
An ALU capable of logical operators, addition, subtraction, shift left, shift right, multiplying, dividing, and other specialised functions
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
"Faster Execution" - Runs instructions on both edges of the clock pulse 
16x16 pixel display with 32 "Sprites" and 15-bit direct colour
Inputs, both "controllers" and keyboards
Random number generator
Text outputs
Stack
Von Neumann Architecture
Assembler (written in an external program)
Save memory
Four pre-written carts to play with

Previous Updates:
Fixed code controlled graphics updates
Made Bootloader clear TTY, Keyboard, and Controller Pushed
Fixed Register ALU instructions
Updated Cart A and Cart B to make use of the Register ALU instructions
Updated the Cart B to respond to the start button on both controllers
Moved to new project to fix issues around searching for projects branched from private projects
Removed unnecessary EEPROM banks from all carts
Removed unnecessary write lines leading to EEPROMs in carts, preventing code from being overwritten during execution
Made Reset clear WRAM and the General Registers
Fixed Keyboard
Added a Bundle Cart that allows you to view all the carts I have made without changing carts (you must reset the console to view another cart)
Fixed bug in standard bank design which wrote data to incorrect addresses
Fixed contention issue with multiplying
Added Annotations to the In Debug

Updates:
Added Snake Player
Added Reset and Power Labels to the relevant buttons

Will have:
More pre-written carts
Bug fixes

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note:
The Flappy Bird high score and the Snake high score are mine. If you want to save your own scores permanently you will have to fork the project. 

General Architecture:
The Femto-4 is a 16-bit computer with variable length instructions that are comprised of multiple 16-bit words. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neumann architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with (and there are a lot of ALU processes). 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers, the, stack, inputs, outputs, and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 100ms, or 10Hz, which is defined as the clock changing state every 50ms, or at a rate of 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high to by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0x0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. It is also paused by the OP Code 0x0001. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for falling edge only (normal speed), 01 for dual edge (double speed), 10 for every other clock pulse (half speed), and 11 for code controlled, where the 0x0001 OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics, reducing lag by reducing the number of changing outputs. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. 

Graphics:
The Femto-4 is capable of driving a 16x16 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. All the sprites are drawn to the screen whenever a graphics update occurs, depending on the graphics mode. When using dual-edge "Faster Execution", the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be a sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed (see how Snake works). The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically decreases the simulation's stack usage. 

ALU:
The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting. This is unlike my previous computer which had different chips for each operation it could do. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the Femto-4's graphics data. 

Conditional Jumps:
The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. 
The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. In theory a similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not.
The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing:
This computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. These pulses can tell registers to write and what source to write from, enable the read and write lines, update the ALU, and update the stack. For more information on how delay works see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction

Other Notes:
The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. This makes it easy to additional chips to the computer. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 






This is a secret to everybody, unless you found it. 


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0 Stars     93 Views
User:

Ejercicio 3 - Clase 3

Ejercicio 3 - Clase 3

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0 Stars     231 Views

4Bit ALU

4Bit ALU
ALU

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2 Stars     653 Views

To simulate a simple 4 BIT ALU circuit


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0 Stars     57 Views
User:

CPU ALU BUILD

CPU ALU BUILD

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0 Stars     13 Views

4 bit adder

4 bit adder
ALU

this is a half bit adder


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0 Stars     65 Views
User:

nalu 100

nalu 100

new: https://circuitverse.org/users/78044/projects/nalu-150

NALU (Nou Arithmetic Logic Unit) Is a ALU that does stuff.

Based off: JCU (in tags)

functions:

0:compare

1:logic

(slots A and B are free function stuff, must have an input and an output of 2 bits, but can have as many outputs as you want connected to it.)

slot functions:

10:slot a

11:slot b


project.name
0 Stars     17 Views
User:

ALU

ALU

This is a basic adder, subtractor and 7seg decoder


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0 Stars     16 Views

ALU16BITS

ALU16BITS
ALU

Tarea 2 Arquitectura y organización de computadores. USM CC. 2021-2


project.name
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Arithmetic And Logic Unit

Arithmetic And Logic Unit

It's a project on ALU(Arithmetic And Logical Unit) containing approximately all the gates. according to select lines multiplexers takes one of the input and then reflects it back as output. 


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Simple 4 Bit Computer

Simple 4 Bit Computer

This is My 4 Bit computer with 6 instructions just like the SAP Computer. :)

Instructions:

00 NOP

1x LDA

2x ADD

3x SUB

ee OUT

ff END

Warning:

This computer cannot calculate more than 2 numbers

This Example Program shows 5+7 and 4-5.

To Program, Set the Reset Bit to 1 and Program the ROM.

To Run the Program, Set the Reset Bit to 0.

The Numbers in the output are in Two's Complement so if the number is more than 7 

than the number will be negative because 7 is the biggest number in 4 bits.


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2 Bit ALU(Logical Unit)

2 Bit ALU(Logical Unit)

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ALU 2bit 4 OPS

ALU 2bit 4 OPS

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2 Bit ALU

2 Bit ALU

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ALU Lab - 4

ALU Lab - 4

ALU Function Table


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MUX ALU

MUX ALU

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Ternary ALU

Ternary ALU

This is an ALU project using Balance Ternary Inputs/Outputs represented as two bit values, 01 = -1, 00 = 0, 10 = 1 for each Ternary digit. 11 is treated as zero also in most cases (mostly in the conditioned Trit sub-units).


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Digital Logic Design, Sequential. Combinational Logic, ALU, CPU, Finite State Machine, FSM, State Diagram, State Table, Flip Flops, Registers, Counters


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1-BIT ALU CIRCUIT

1-BIT ALU CIRCUIT

Simple Arithmetic Logic Unit


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Lab MUX y ALU

Lab MUX y ALU

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TP Portes logiques ALU - PB

TP Portes logiques ALU - PB

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1-bit ALU Sample Test

1-bit ALU Sample Test
ALU

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Complessivo_009

Complessivo_009
ALU

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Proyecto-ArquiChismosos

Proyecto-ArquiChismosos

Realizado por:

Ana Sofia Rodríguez Martínez

Paola Benitez Ruiz

César Andrés Olarte Marín

Este es el primer proyecto de la clase Arquitectura del Computador. Para este proyecto se desarrollo un ALU con entradas de 5 bits.



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my_alu

my_alu
ALU

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ALU H&amp;H DD&amp;CA

ALU H&amp;H DD&amp;CA
ALU

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Decoder Multiplexor

Decoder Multiplexor

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ALU

ALU
ALU

Create a simple ALU that performs an arithmetic operation (sum of two bits) and three logic operations (AND, NOR and XOR). Use a multiplexer that selects only one operation. aluminum ALU implementation with the Circuitverse ALU or with logical circuit.


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User Image Mel

4-Bit Adder Subtractor

4-Bit Adder Subtractor

A 4-Bit Adder-Subtractor. It adds and subtracts


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This is a Hexadecimal ALU with 6 status flags!

UF and OF are underflow and overflow respectivly 


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Adders

Adders

All adders up to 16-Bit


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RECOMMENDED FOR COMPUTERS 

This is the second addition of the B8 Series. Otherwise known as the BURTONABLE 8 256 it is capable of running programs 256 lines long! as well as 7 instructions to use

LDA 0001: Loads the given value into the Accumulator

ADD 0010: The given value will be added to the accumulator

SUB 0011: The given value will be subtracted from the accumulator

OUT 1110: Shows the output of A and B

HALT 1111: Stops all

PRT 0110: Prints a 7 bit ASCII character to the TTY

CLRTTY 0101: Clears the TTY element

DRAW BLACK 1001: Draws the color black to the X (4 bits) and the Y (4 bits)

DRAW WHITE 1011: Draws the color white to the X (4 bits) and the Y (4 bits)

JC 1100: Only jumps up by the given data if 2 negative numbers add up to a positive number

sometimes the codes get corrupted just spam reset a couple times

FUN CODES: To use them, just double click the EEPROM

To retrieve a code just press the save button and then open the dev console (FN + Volume up MAC) or F12 (PC)

To put codes in the EEPROM double click it and paste the code

circle.

2952,2968,2984,2999,2998,2997,2980,2964,2948,2933,2934,2935,1635,1641,1650,1635,1644,1637,3840,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

I would love to see your codes too so post them in the comments!

THIS VERSION IS OUTDATED HERE IS THE LINK TO THE NEW ONE https://circuitverse.org/users/160624/projects/b8256-v3

Oh and also The original B8 got deleted :(


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8-Bit Computer

8-Bit Computer

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USE ON A COMPUTER

Same as V2 exempt that there is a Jump if zero command

JO: Jumps if the ALU output is 0

And you can under stand things better!

(these instructions arent done)


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A collection of binary adders with Binary, Hex, and Decimal input and output representation


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Simple 1 bit ALU with 4 operations

Simple 1 bit ALU with 4 operations

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8-bit Arithmetic Logic Unit (2

8-bit Arithmetic Logic Unit (2

A simple 8-bit arithmetic logical unit.

The following commands are implemented:

Logic Operations:
[0] 000: OR
[1] 001: NAND
[2] 010:NOR
[3] 011: AND
Arithmetic Operations:
[4] 100: ADD
[5] 101: SUB

The two's complement for subtraction is implemented with a NOT Gate and an adder (which simply adds 1 to the negated input).


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8-bit Arithmetic Logic Unit (ALU)

8-bit Arithmetic Logic Unit (ALU)

A simple 8-bit arithmetic logical unit.

The following commands are implemented:

Logic Operations:
[0] 000: OR
[1] 001: NAND
[2] 010:NOR
[3] 011: AND
Arithmetic Operations:
[4] 100: ADD
[5] 101: SUB

The two's complement for subtraction uses the built in component.


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Project 1

Project 1
ALU

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Session06-ALU

Session06-ALU

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Practical10

Practical10
ALU

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ALU

ALU

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APU 23 Combinatorio

APU 23 Combinatorio

Circuitos combinacionales para una ALU simple


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4 bit binary adder

4 bit binary adder

Hey, i built a 4 bit Adder circuit which can add a pair of 4 bit binary numbers. it consist of 7 XOR gates, 7 AND gates, and 3 OR gates


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Logic test

Logic test
ALU

Test;)


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ALU-CINATE

ALU-CINATE

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Simple Computer and all needed for it


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Design of Arithmetic Logic Unit

Design of Arithmetic Logic Unit
ALU

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition, subtraction, division, multiplication and logical operations like and, or, xor, nand, nor etc. A simple block diagram of a 4 bit ALU for operations and,or,xor and Add is shown here :


The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1 and S0 the circuit operates as follows:

for Control signal S1 = 0 , S0 = 0, the output is A And B,

for Control signal S1 = 0 , S0 = 1, the output is A Or B,

for Control signal S1 = 1 , S0 = 0, the output is A Xor B,

for Control signal S1 = 1 , S0 = 1, the output is A Add B..



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ALU

ALU
ALU

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HECK CPU(incomplete)

HECK CPU(incomplete)

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CPU! Finally!

CPU! Finally!

A CPU! this took me a while to figure out, mostly how to get it to run comands, but I eventually found a solution of using 4 bits as function indicators, 4 as where to save the output, 4 as the 2nd input, and 4 as the first input!


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ALU 1-bit

ALU 1-bit
ALU

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4 Bit ALU

4 Bit ALU

4-Bit ALU

The ALU supports AND, OR, ADD, SUB, BLT, and SLT instructions

Can add, subtract, AND, OR, compare if equal, compare if less than, and detect overflow


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The Hack Computer

The Hack Computer
ALU

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1 Bit ALU

1 Bit ALU

1 Bit ALU that supports AND, OR, ADD, and SUB

Op Codes:

00 - AND

01 - OR

10 - ADD

10 - SUB (Binvert = 1, CarryIn = 1)


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Add/Subrtract

Add/Subrtract

Features a single-bit adder and subtractor as well as a combination of the two. Also showcases a 4-bit adder/subtractor and an 8-bit ALU adder subtractor.


(If anything in the description is wrong please feel free to say so in the comments.


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Untitled

Untitled
ALU

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2-BIT ALU

2-BIT ALU

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2 bit ALU

2 bit ALU
ALU

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8-Bit ALU

8-Bit ALU

Some 8-Bit ALU I made for fun lol


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Simple 8-Bit ALU

Simple 8-Bit ALU

Made this for my FEMBOY-8 CPU


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Simple ALU (Built-In Adder)

Simple ALU (Built-In Adder)
ALU

Random thing I made


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Functional Electronic Machine Binary Operator Yes - 8-bit cpu

Working on a NEW CPU: Femboy-16!


ASSEMBLER:

https://output.jsbin.com/wutikij


INSTRUCTION SET:
00: NOP - Nothing
01: HLT - Halt program
02: OUT [id] - Output the accumulator out of an output
03: LDI A, [d8] - Loads immediate 8 bit word into the accumulator
04: MOV [r], A - Move register to accumulator
05: MOV A, [r] - Move accumulator to register
06: INC [r] - Increment a register
07: DEC [r] - Decrememt a register
08: ADD [r], A - Add the accumulator from a register
09: SUB [r], A - Subtract the accumulator from a register
0A: AND [r], A - And the register and accumulator
0B: IOR [r], A - OR the register and accumulator
0C: XOR [r], A - XOR the register and accumulator
0D: NOT [r] - NOT a register
0E: SRR [r] - Barrel shift accumulator right
0F: SRL [r] - Barrel shift accumulator left
10: JUP [d8] - Jump to a location
11: JPP [r] - Jump to a register value
12: JPL A, [d8] - Jump if accumulator is less than 0
13: JZO A, [d8] - Jump if accumulator is 0
14: JPG A, [d8] - Jump if accumulator is greater than 0
15: JLE A, [d8] - Jump if accumulator is less than or equal to 0
16: JGE A, [d8] Jump if accumulator is greater than or equal to 0
17: JNZ A, [d8] Jump if accumulator is not 0
18: CLR [r] - Clear a register
19: INP [id] - Store INPUT id in accumulator
1A: MOV pA, [r] - Move the value at address A register r
1B:  MOV [r], pA - Move register r into address A
1C: MOV [p], A - Move a value in a pointer to the accumulator
1D: MOV A, [p] - Move the accumulator to a location
1E: MLT [r], A - Multiply register r by the accumulator
1F: DIV [r], A - Divide register r by accumulator


REGISTERS:
00: 
REGISTER 1
01: REGISTER 2
02: REGISTER 3
04: REGISTER 4
05: ZERO FLAG (R)
06:
PC (R)
07: ALU Result (R)


Update Notes:
So this is the 4th iteration of my CPU lol... I added a few programs for you all to try out and you can even use an assembler now!


To-Do:
Increase amount of registers to 8
Make a simple command line
Make an assember
Make a simple operating system for the CPU
Add rgb output


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Untitled

Untitled

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0 Stars     1 Views

Vanshika garg

Vanshika garg
ALU

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About the Combinox R1:

This is the third 16-bit CPU I have made. Its new name was inspired by the new combinational code. It is also my first computer to feature a graphics and base ten display. As a result of its brand new architecture, code, and clock it is much faster than my previous CPUs. 

Directions for use:

Choose the desired EEPROM program and insert it into the slot. First press the "RESET" button. Now press the "ON" button and enjoy your program.

Descriptions of programs:

blank: A blank EEPROM to be coded.

2+2: Calculates two plus two and then displays the result on the number display.

count up forever: Counts up by one until it reaches 65,535 then loops back to 0.

transfer from keyboard to display: Displays the ascii value of whatever key is being entered on the keyboard.

random noise: Displays random noise on the screen.

Credits:

Sanderokian Stfetoneri - clock

Sanderokian Stfetoneri - 16 bit division


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2-Bit Arithmetic Logic Unit by Mohammad Salman, ID: 201-15-14165

2-Bit Arithmetic Logic Unit by Mohammad Salman, ID: 201-15-14165

2-Bit Arithmetic Logic Unit design by Mohammad Salman, ID: 201-15-14165


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FEMBOY-8v1.1

FEMBOY-8v1.1

Functional Electronic Machine Binary Operator Yes - 8-bit cpu

This is a work in progress right now.


INSTRUCTION SET:
00:
MOV [r], A - Loads a register into the accumulator.
01: MOV A, [r] - Saves a register into the accumulator.
02: INC [r] - Increment a register 
03: DEC [r] - Decrement a register
04: ADD [r] - Add the accumulator to a register
05: SUB [r] - Subtract the accumulator to a register
06: OUT [r] - Output a signal from a register
07: HLT - End program


REGISTERS:
00:
REGISTER 1
01: REGISTER 2
02: REGISTER 3
04: REGISTER 4


Update Notes:
Final design before update of is a.


To-Do:
Add WIP instructions
Add the accumulator to a register address
Increase amount of registers to 8
Add Ram manipulation instructions
Add Input to CPU
Add more operations to the ALU
Add ASCII i/o
Make a simple command line
Make an assember
Make a simple operating system for the cpu
Add rgb output


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8-Bit ALU

8-Bit ALU

This is the ALU that i'm using on my computer the Femboy 8 Here,
it includes an Adder, Subtractor, Logical operations, Shift, Rotate, and Comparison.


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Functional Electronic Machine Binary Operator Yes - 8-bit cpu

This is a work in progress right now.


INSTRUCTION SET:
00: NOP - Nothing
01: HLT - Halt program
02: OUT [r] - Output a register
03: LDA [d8] - Loads 8 bit data into the accumulator
04: MOV [r], A - Move register to accumulator
05: MOV A, [r] - Move accumulator to register
06: INC [r] - Increment a register
07: DEC [r] - Decrememt a register
08: ADD [r], A - Add the accumulator from a register
09: SUB [r], A - Subtract the accumulator from a register
0A: AND [r], A - And the register and accumulator
0B: IOR [r], A - OR the register and accumulator
0C: XOR [r], A - XOR the register and accumulator
0D: NOT [r] - NOT a register
0E: SRR [r] - Shift register right
0F: SRL [r] - Shift register Left


REGISTERS:
00: 
REGISTER 1
01: REGISTER 2
02: REGISTER 3
04: REGISTER 4


Update Notes:
The instruction set now has 16 instructions with logic operations, loading, shift, and nop. 


To-Do:
Add WIP instructions
Add the accumulator to a register address
Increase amount of registers to 8
Add Ram manipulation instructions
Add Input to CPU
Add more operations to the ALU
Add ASCII i/o
Make a simple command line
Make an assember
Make a simple operating system for the cpu
Add rgb output


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Max circuit


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Untitled

Untitled

Just a thing I'm planning on using for conditional jumps


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4-bit Multiplier (No Overflow)

4-bit Multiplier (No Overflow)

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4-bit Multiplier

4-bit Multiplier

Yay overflow


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NandGame ALU

NandGame ALU

Just the 16 bit ALU from NandGame


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NandGame CPU

NandGame CPU

A port of the NandGame CPU into CircuitVerse


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2 Stars     5 Views
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Half-Precision Simple FPU

Half-Precision Simple FPU

Just a basic fpu with multiply, subtract, and add


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Functional Electronic Machine Binary Operator Yes - 8-bit cpu

This is a work in progress right now.


INSTRUCTION SET:
00: NOP - Nothing
01: HLT - Halt program
02: OUT [id] - Output the accumulator out of an output
03: LDI A, [d8] - Loads immediate 8 bit word into the accumulator
04: MOV [r], A - Move register to accumulator
05: MOV A, [r] - Move accumulator to register
06: INC [r] - Increment a register
07: DEC [r] - Decrememt a register
08: ADD [r], A - Add the accumulator from a register
09: SUB [r], A - Subtract the accumulator from a register
0A: AND [r], A - And the register and accumulator
0B: IOR [r], A - OR the register and accumulator
0C: XOR [r], A - XOR the register and accumulator
0D: NOT [r] - NOT a register
0E: SRR [r] - Shift register right
0F: SRL [r] - Shift register Left
10: JUP [d8] - Jump to a location
11: JPP [r] - Jump to a register value
12: JPL A, [d8] - Jump if accumulator is less than 0
13: JZO A, [d8] - Jump if accumulator is 0
14: JPG A, [d8] - Jump if accumulator is greater than 0
15: JLE A, [d8] - Jump if accumulator is less than or equal to 0
16: JGE A, [d8] Jump if accumulator is greater than or equal to 0
17: JNZ A, [d8] Jump if accumulator is not 0
18: CLR [r] - Clear a register
19: INP [id] - Store INPUT id in accumulator
1A: MOV pA, [r] - Move the value at address A register r
1B:  MOV [r], pA - Move register r into address A
1C: MOV [p], A - Move a value in a pointer to the accumulator
1D: MOV A, [p] - Move the accumulator to a location
1E: MLT [r], A - Multiply register r by the accumulator
1F: DIV [r], A - Divide register r by accumulator


REGISTERS:
00: 
REGISTER 1
01: REGISTER 2
02: REGISTER 3
04: REGISTER 4
05: ZERO FLAG (R)
06: 
PC (R)
07: ALU Result (R)


Update Notes:
Welcome to the 3rd iteration of my Femboy-8 CPU! This might be the last version with 32 instructions.


To-Do:
Increase amount of registers to 8
Make a simple command line
Make an assember
Make a simple operating system for the CPU
Add rgb output


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Femboy-16

Femboy-16

Femboy-16

Functional Electronic Machine Binary Operator Yes

A 16 bit CPU by Kain and Pacifiky


ABOUT

Made as a Successor to the FEMBOY-8.


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Functional Electronic Machine Binary Operator Yes - 8-bit cpu

Working on a new CPU: Femboy-16


ASSEMBLER:

https://output.jsbin.com/wutikij


INSTRUCTION SET:
00: NOP - Nothing
01: HLT - Halt program
02: OUT [id] - Output the accumulator out of an output
03: LDI A, [d8] - Loads immediate 8 bit word into the accumulator
04: MOV [r], A - Move register to accumulator
05: MOV A, [r] - Move accumulator to register
06: INC [r] - Increment a register
07: DEC [r] - Decrememt a register
08: ADD [r], A - Add the accumulator from a register
09: SUB [r], A - Subtract the accumulator from a register
0A: AND [r], A - And the register and accumulator
0B: IOR [r], A - OR the register and accumulator
0C: XOR [r], A - XOR the register and accumulator
0D: NOT [r] - NOT a register
0E: SAR [d8] - Barrel shift accumulator right
0F: SAL [d8] - Barrel shift accumulator left
10: JUP [d8] - Jump to a location
11: JPP [r] - Jump to a register value
12: JPL A, [d8] - Jump if accumulator is less than 0
13: JZO A, [d8] - Jump if accumulator is 0
14: JPG A, [d8] - Jump if accumulator is greater than 0
15: JLE A, [d8] - Jump if accumulator is less than or equal to 0
16: JGE A, [d8] Jump if accumulator is greater than or equal to 0
17: JNZ A, [d8] Jump if accumulator is not 0
18: CLR [r] - Clear a register
19: INP [id] - Store INPUT id in accumulator
1A: MOV pA, [r] - Move the value at address A register r
1B:  MOV [r], pA - Move register r into address A
1C: MOV [p], A - Move a value in a pointer to the accumulator
1D: MOV A, [p] - Move the accumulator to a location
1E: MLT [r], A - Multiply register r by the accumulator
1F: DIV [r], A - Divide register r by accumulator


REGISTERS:
00: REGISTER 1
01: REGISTER 2
02: REGISTER 3
04: REGISTER 4
05: ZERO FLAG (R)
06: PC (R)
07: ALU Result (R)


Update Notes:
So this is the 4th iteration of my CPU lol... I added a few programs for you all to try out and you can even use an assembler now!


To-Do:
Increase amount of registers to 8
Make a simple command line
Make an assember
Make a simple operating system for the CPU
Add rgb output


project.name
0 Stars     8 Views

Primer proyecto - ALU

Primer proyecto - ALU

Steven Bohorquez
Juan Uribe
Juan Bernal