project.name

noulmao

Member since: 97 days

Educational Institution: ness

Country: United States

Hex outputs with output numbers

Hex outputs with output numbers
Public
Hex outputs with output numbers
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rom

rom
Public
rom
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binary counter

binary counter
Public
binary counter
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binary random

binary random
Public
binary random
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ROM test 11037

ROM test 11037
Public
ROM test 11037
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14 16-bit digit outputs (with text)

14 16-bit digit outputs (with text)
Public
14 16-bit digit outputs (with text)
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Untitled1

Untitled1
Public
Untitled1
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decoder and multiplexer original

decoder and multiplexer original
Public
decoder and multiplexer original
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decoder and multiplexer

decoder and multiplexer
Public
decoder and multiplexer
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Binary password generator

Binary password generator
Public
Binary password generator
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ez

ez
Public
ez
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ROM2

ROM2
Public
ROM2
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VENDING MACHINE 2.0

VENDING MACHINE 2.0
Public
VENDING MACHINE 2.0
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faster keyboard

faster keyboard
Public
faster keyboard
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Simple Decade Counter 2.0

Simple Decade Counter 2.0
Public
Simple Decade Counter 2.0
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Binary counter

Binary counter
Public
Binary counter
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closed current

closed current
Public
closed current
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splitter test

splitter test
Public
splitter test
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simple binary adding system

simple binary adding system
Public
simple binary adding system
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simple binary adding system 2

simple binary adding system 2
Public
simple binary adding system 2
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looooooooong splitter

looooooooong splitter
Public
looooooooong splitter
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simple binary adder (NO ROM)

simple binary adder (NO ROM)
Public
simple binary adder (NO ROM)
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simple counter

simple counter
Public
simple counter
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matrix test

matrix test
Public
matrix test
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tunnel and flag

tunnel and flag
Public
tunnel and flag
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random rom adder

random rom adder
Public
random rom adder
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Reyes, Glesica 2.0

Reyes, Glesica 2.0
Public
Reyes, Glesica 2.0
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haha yes

haha yes
Public
haha yes
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random generators

random generators
Public
random generators
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LED calculator

LED calculator
Public
LED calculator
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Memory cell

Memory cell
Public
Memory cell
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UntitledTest

UntitledTest
Public
UntitledTest
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Calculator

Calculator
Public
Calculator
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SUBTARCT

SUBTARCT
Public
SUBTARCT
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Adder with roms

Adder with roms
Public
Adder with roms
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Untitled

Untitled
Public
Untitled
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Registers

Registers
Public
Registers
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flag and tunnel generators

flag and tunnel generators
Public
flag and tunnel generators
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UntitledANDgatetest

UntitledANDgatetest
Public
UntitledANDgatetest
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Color Picker

Color Picker
Public
Color Picker
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stepper

stepper
Public
stepper
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no

no
Public
no
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32

32
Public
32
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2's complement hex

2's complement hex
Public
2's complement hex
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Small computer system

Small computer system
Public
Small computer system
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Small thing

Small thing
Public
Small thing
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{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}

{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}
Public
{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit 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Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}{"layout":{"width":100,"height":140,"title_x":50,"title_y":13,"titleEnabled":true},"verilogMetadata":{"isVerilogCircuit":false,"isMainCircuit":false,"code":"// Write Some Verilog Code Here!","subCircuitScopeIds":[]},"allNodes":[{"x":40,"y":0,"type":0,"bitWidth":4,"label":"","connections":[]}],"id":93913114779,"name":"Subcircuit Main","Output":[{"x":1070,"y":250,"objectType":"Output","label":"","direction":"LEFT","labelDirection":"RIGHT","propagationDelay":0,"customData":{"nodes":{"inp1":0},"constructorParamaters":["LEFT",4,{"x":100,"y":20,"id":"2wz899zwLIsGNqJHVRkQ"}]}}],"restrictedCircuitElementsUsed":[],"nodes":[],"scopes":[],"logixClipBoardData":true}
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Adder and subtractor

Adder and subtractor
Public
Adder and subtractor
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Adder and subtractor

Adder and subtractor
Public
Adder and subtractor
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Every gate with a NOT gate

Every gate with a NOT gate
Public
Every gate with a NOT gate
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Long Decoder

Long Decoder
Public
Long Decoder
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FLAG TEST

FLAG TEST
Public
FLAG TEST
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Keyboard passcode lock

Keyboard passcode lock
Public
Keyboard passcode lock
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Another decoder with a lot of OR gates

Another decoder with a lot of OR gates
Public
Another decoder with a lot of OR gates
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Connect one

Connect one
Public
Connect one
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Play Roulette / Programable Computer

Play Roulette / Programable Computer
Public
Play Roulette / Programable Computer
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Rolling game

Rolling game
Public
Rolling game
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Calculator (WIP)

Calculator (WIP)
Public
Calculator (WIP)
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calculator

calculator
Public
calculator
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3-Bit Binary Carry look-ahead Adder

3-Bit Binary Carry look-ahead Adder
Public
3-Bit Binary Carry look-ahead Adder
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Numberpad input with display

Numberpad input with display
Public
Numberpad input with display
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Adder with Addons

Adder with Addons
Public
Adder with Addons
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Subtractor Decoder

Subtractor Decoder
Public
Subtractor Decoder
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CPU Microprocessor

CPU Microprocessor
Public
CPU Microprocessor
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Counter

Counter
Public
Counter
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nine.

nine.
Public
nine.
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8-bit register

8-bit register
Public
8-bit register
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NOU V.1

NOU V.1
Public
NOU V.1
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Computer

Computer
Public
Computer
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Byte RAM

Byte RAM
Public
Byte RAM
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NOU V.2

NOU V.2
Public
NOU V.2
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NOU V.3

NOU V.3
Public
NOU V.3
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NOU V.4

NOU V.4
Public
NOU V.4
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wanna see me speedrun?

wanna see me speedrun?
Public
wanna see me speedrun?
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double letter

double letter
Public
double letter
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Logic.ly BUS thing

Logic.ly BUS thing
Public
Logic.ly BUS thing
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2's complement and decoder adder

2's complement and decoder adder
Public
2's complement and decoder adder
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Largest RAM module! 2816B!

Largest RAM module! 2816B!
Public
Largest RAM module! 2816B!
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Small but big computer

Small but big computer
Public
Small but big computer
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Takeover

Takeover
Public
Takeover
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Computer?

Computer?
Public
Computer?
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Hex adder / decoder

Hex adder / decoder
Public
Hex adder / decoder
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Lambda

Lambda
Public
Lambda
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challenge

challenge
Public
challenge
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keyboard

keyboard
Public
keyboard
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32 bit adder

32 bit adder
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32 bit adder
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Every misc item

Every misc item
Public
Every misc item
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nothing...

nothing...
Public
nothing...
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8-bit control adder

8-bit control adder
Public
8-bit control adder
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31+1 bit adder

31+1 bit adder
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31+1 bit adder
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4 bit adder

4 bit adder
Public
4 bit adder
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var led

var led
Public
var led
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Error

Error
Public
Error
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NOU FINAL VER

NOU FINAL VER
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NOU FINAL VER
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nothing...

nothing...
Public
nothing...
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Adder and subtractor calculator

Adder and subtractor calculator
Public
Adder and subtractor calculator
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error noob

error noob
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error noob
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2 things

2 things
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2 things
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Compass

Compass
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Compass
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RAM saving

RAM saving
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RAM saving
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A easy Gate puzzle(s)

A easy Gate puzzle(s)
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A easy Gate puzzle(s)
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Easy and Fast addition calculator

Easy and Fast addition calculator
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Easy and Fast addition calculator
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Every LED

Every LED
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Every LED
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The Reznor circuit team (AD)

The Reznor circuit team (AD)
Public
The Reznor circuit team (AD)
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another simple calculator

another simple calculator
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another simple calculator
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all inputs

all inputs
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all inputs
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sandbox

sandbox
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sandbox
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1 Digit binary calculator

1 Digit binary calculator
Public
1 Digit binary calculator
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computer (beta)

computer (beta)
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computer (beta)
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Long Decoder

Long Decoder
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Long Decoder
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6line-64line decoder

6line-64line decoder
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6line-64line decoder
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collab

collab
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collab
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RAM saving

RAM saving
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RAM saving
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Untitled

Untitled
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Untitled
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RPS

RPS
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RPS
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Simple Decade Counter/Timer

Simple Decade Counter/Timer
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Simple Decade Counter/Timer
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CHALLENGE

CHALLENGE
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CHALLENGE
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assignment 10

assignment 10
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assignment 10
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simple binary adding system

simple binary adding system
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simple binary adding system
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simple binary adding system 2

simple binary adding system 2
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simple binary adding system 2
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simple binary adder (NO ROM)

simple binary adder (NO ROM)
Public
simple binary adder (NO ROM)
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Computer?

Computer?
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Computer?
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collab

collab
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collab
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