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Searched Tags: computer

But How Do It Know

Tags: computer
But How Do It Know

Bitwise-only computer

A new addition to my computer design collection, with a few ideas I've toyed around with for CPU design. I'll probably implement these ideas in my Simple Computer design later this summer, 2020.

Bitwise-only computer

super simple 8 bit computer

that's nice
super simple 8 bit computer


Tags: computer
8-Bit Computer
Basic Universal Computer

Computer Exponential Code Demo

A Computer. Kind of.

This version is setup to demonstrate a program that puts input A to the power of input B This version has been specifically modified to make demonstrating the program easier. This was done by making operand A for the first two instructions depend on user input, which allows the user to easily test the program with different values. Note: X^0 does not work due to the fact the the output value (address 5) is never written to. 
The code is as follows:
00: LOAD Input A into Address 00
01: LOAD Input B into Address 01
02: LOAD1F into Address 02
03: XOR Addresses 00 and 02
04: LOAD XOR Result into Address 03
05: XOR Addresses 01 and 02
06: LOAD XOR Result into Address 04
07: LOAD 01 into 00
08: LOAD 00 into 08
09: LOAD 01 into 02
0A: LOAD 01 into 06
0B: ADD 04 and 06
0C: IF ADD Result = 00, GOTO 1B, ELSE GOTO 0D
0D: LOAD 00 into 05
0E: LOAD 01 into 07
0F: ADD Addresses 03 and 07
10: IF ADD Result = 00, GOTO 16, ELSE GOTO 11
11: ADD Addresses 00 and 05
12: LOAD ADD Result into 05
13: ADD 02 and 07
14: LOAD ADD Result into 07
15: GOTO 0F
16: ADD 02 and 06
17: LOAD ADD Result into 06
18: ADD 05 and 08
19: LOAD ADD Result into 00
1B: RETURN Address 05

32-Bits of 5-bit RAM,
32 Lines for Instructions,
ADD, AND and XOR Functions.
Go To Functionality
Can do IF = Statements

OP Codes:
0000 = Nothing
0001 VVVVV AAAAA = LOAD VVVVV into address AAAAA
0010 AAAAA 00000 = LOAD Add result into address AAAAA
0011 DDDDD VVVVV = ADD DDDDD and VVVVV together
0100 AAAAA BBBBB = ADD address AAAAA and address BBBBB together
0101 DDDDD VVVVV = AND DDDDD and VVVVV together
0110 AAAAA BBBBB = AND address AAAAA and address BBBBB together
0111 DDDDD VVVVV = XOR DDDDD and VVVVV together
1000 AAAAA BBBBB = XOR address AAAAA and BBBBB together
1001 AAAAA 00000 = LOAD AND result into address AAAAA
1010 AAAAA 00000 = LOAD XOR result into address AAAAA
1011 AAAAA 00000 = GOTO address AAAAA (in instruction memory) 
1100 AAAAA BBBBB = If add result = 0 (ignoring carry), GOTO address AAAAA else go to address BBBBB (in instruction memory)
1101 VVVVV 00000 = Return VVVVV (Stops the program)
1110 AAAAA 00000 = Return the value at address AAAAA (Stops the program)
1111 = Nothing
Computer Exponential Code Demo


SAP-1 ("Simple As Possible")

A simple 8-bit processor. It has a simple instruction set:
  • LDA - 0 - Load RAM data into accumulator
  • ADD - 1 - Add RAM data to accumulator
  • SUB - 2 - Subtract RAM data from accumulator
  • OUT - e - Load accumulator data into output register
  • HLT - f - Stop processing
Credits to the book "Digital Computer Electronics" by Albert Paul Mauvino, where he invented the educational processor.


wip computer i doubt ill finish
Tags: computer


WIP computer!
Tags: computer


If you have any questions about this or other designs, feel free to shoot me an email at [email protected] I don't check it very often (since it's a secondary account), and you may not receive a reply for around a week.

A simple computer with an added RAM module. A work in progress, with much more I want to add, such as bitwise operators, a larger bus size, data type support including unsigned and signed integers, floating point numbers, conditional instructions, and more. There are two programmed versions, one that calculates the fibonacci sequence, and the other uses conditional instructions to determine whether it should increment a number, or halt the program. And there is also the first design I've made, which has a lot of unneeded parts in it.

UPDATE 1: added a jump instruction to allow loops and other useful applications.

UPDATE 2: Made a second version of the design, and made a better instruction set for it, removed the Memory register, since it's totally unnecessary with a RAM module. The second version also calculates the Fib sequence.

UPDATE 3: Added signed integer addition and subtraction support to version 2. Of course, this limits the positive range of integers to 127, rather than 255, but c'est la vie, I'm going to expand the size of the bus anyway.

UPDATE 4: Version 2 is temporarily down, since I'm finally adding bitwise operator functions to the ALU.

UPDATE 5: Version 2 is now back in action, with some added functions such as increment and decrement by 1, as well as left bit shifting. The ALU still needs some more work, since I'm having trouble implementing a right bit shift function. Once I have bit shifting working, I might make a program that can multiply using the shift/add method.

UPDATE 6: Version 2 now has magnitude comparison and bit-shifting functions. Conditional jumps still in the works.

UPDATE 7: Version 2 finally has a conditional jump register. It can be loaded with a Boolean from either RAM or the ALU, or directly set to either 1 or 0 by way of a set instruction. I still need to add a flag register to the design, so it can detect overflows (and maybe in the future, interrupts).

BONUS UPDATE: After a few months of studying processor and computer design, I discovered that I've unwittingly designed a Von-Neumann architecture computer (as opposed to the Harvard architecture. Reference Wikipedia if these terms are unfamiliar). Frankly, I went into this project relatively blind, and just a week ago discovered that this kind of design had a name. Well, the more you know.

UPDATE 8: I've created a new CPU design, some of which I will implement into this main circuit later this summer.  Here's the link to that design: Also, I plan to overhaul the entire design to minimize cycle inefficiencies.

Tags: computer
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