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4 Bit Asynchronous Counter using JK Flip-FLop

Anyway, This is a circuit where I'm using a Priority Encoder to do this. When you press the change button 2 times of actually turning it off, it will say "set" then, After 6 seconds, the "set" word will be gone. (Bonus: The binary shows up in two different ways. 1. Shows up as the 7 SEG Display's Dot. 2. Shows up as a 3-bit output.)

Digital Logic Design, Sequential. Combinational Logic, ALU, CPU, Finite State Machine, FSM, State Diagram, State Table, Flip Flops, Registers, Counters

Counters and timing signal generators discussed in the Computer Science and Computer Architectures [CSCA] course at the University of Applied Sciences CAMPUS 02, Graz, Austria.

The project features the following circuits:

• Sample 2-Bit Counter - a simple counter exploratory developed by students during the lectures.
  
• Sample 2-Bit Counter with Timing Signals - that simple counter extended with decoder to provide timing signals.
• 2-Bit Switch-Tail Ring Counter - developed by using D flip-flops.
• 2-Bit Johnson Counter - developed by extending the 2-Bit Switch-Tail Ring Counter with decoder to provide timing signals.
• 4-Bit Switch-Tail Ring Counter - developed by extending the 2-Bit Switch-Tail Ring Counter with two more D flip-flops. [learn more (see chapters at the bottom of the page)]
• 4-Bit Johnson Counter - developed by extending the 4-Bit Switch-Tail Ring Counter with decoder to provide timing signals. [learn more (see chapters at the bottom of the page)]

Experiment 4 Synchronous and Asynchronous Counters