Project
New Project
Save Online
Save Offline
Open Offline
Clear Project
Recover Project
Preview Circuit
View Previous UI
Circuit
New Circuit +
New Verilog
Module
Insert SubCircuit
Tools
Combinational
Analysis
Hex-Bin-Dec
Converter
Download Image
Themes
Custom Shortcut
Export Verilog
Help
Tutorial Guide
User Manual
Learn Digital Logic
Discussion Forum
Untitled
-
+
Sign In
+
Circuit Elements
Layout Elements
Timing Diagram
1 cycle =
Units
Testbench
Test:
Type:
Edit
Remove
Group:
Case:
LABELS
Bitwidth
Current Case
Result
Validate
Run All
placeholder
Tests Passed
View Detailed
No Test is attached to the current circuit
Attach Test
Verilog Module
Reset Code
Save Code
This is an experimental module. The code is not saved unless the "Save Code" button is clicked.
Apply Themes
Select a theme:
default
solarized
elegant
neat
idea
neo
blackboard
cobalt
night
the-matrix
midnight
monokai
Properties
Layout
Width
Height
Reset all nodes:
Title
Title Enabled:
Save
Cancel
PNG
JPEG
SVG
BMP
GIF
TIFF
Full Circuit View
Current View
Transparent Background
Resolution:
1x
2x
4x
Paste
Copy
Cut
Delete
Undo
New Circuit
Insert SubCircuit
Center Focus
Decimal value
Binary value
Binary-coded decimal value
Octal value
Hexadecimal value
Report an issue
×
Report an issue
Describe your issue:
Email
[Optional]
:
Report