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Tags: Verilog

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Verilog Gates

Verilog Gates

just gates written in Verilog (if you want it to work, you will need to fork it, and then go and save the code for each gate, it for some reason breaks everything when I save the thing)


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First Verilog :)

First Verilog :)

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VerilogTest

VerilogTest

Attempt to create and integrate a verilog module.


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Simple ALU using Verilog code