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This is a CPU witch is capable of executing a lot of stuff in one clock cycle, and this CPU can shift left up to 7 times and shift right up to 7 times witch means that it is possible to  multiply and divide in one clock cycle if you program a table in the program memory. it has a 32 bit instruction width and a 8 bit address. it also has 

The ALU has the following operations:

• ADD
• SUBTRACT
• SHIFT_LEFT (up to 7 times per cycle 3 bit)
  
• SHIFT_RIGHT (up to 7 times per cycle 3 bit)
  
• XOR
• OR
• NOT

This Was made by miles

Circuit to left-shift an 8-bit number by 0-7 bits! :D

Quick attempt at replicating my barrel-shifter, on freedom.is/svg/barrel-roll.htm

Numerous mysterious contention errors, often varying between runs. At first, I thought I had got my MUXes and DEMUXes confused (they are often implemented as the same circuit, after all), and double-checked those. But that only fixed one error.

Most of those errors, turned out to be from copying the format of my inputs, to serve as outputs: The simulator doesn't like inputs being used as outputs! (This actually is reasonable.) That, and my wiring of the final stage turned out to be wrong (rewired).

I realised my I/O copying error, while editing my simplest barrel shifter, which I forked from this one.

No errors generated anymore, but tests show the circuit isn't working as intended yet (apart from simple shifting), probably due to a copying error: The MUXes & DEMUXes can't be flipped/rotated to work as expected, so I inverted their control inputs for the banked ones, and swapped their outputs for the ones used as logic. This sort of thing tends to complicate transcribing. (I'll have to re-check the copying accuracy another day, as I've run out of time for this now.)

Quick attempt at replicating my simplest barrel-shifter, on freedom.is/svg/roll-left.htm

This is forked from my sophisticated shifter, rather than the other way around... This actually aided the debugging of the more-complex circuit. This one appears to work now: It's always nice to run additional validation.