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Tags: processor

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x80 - Rebused Instructions Set Computer

Draft bus controller for https://github.com/Alikberov/x80

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fox-1-1

The fox-1-1 is the first of the fox-1 series of processors. Like other foxes, the fox-1 type aims for simplistic circuitry and programming.

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16-bit uCISC Processor

This is an example implementation of the uCISC instruction set as defined at https://github.com/grokthis/ucisc. So far it implements the Copy and ALU instructions. Note that multiplication, division and floating point ALU operations are not currently supported. This processor is enough to execute real programs.

The EEPROM is programmed with the fibonacci calculation found in the uCISC examples.


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pixy


pixy is a simple 32-bit processor with twelve instructions.

pixy can...

here are the instructions:

  • add <rn>, <rs | value>
  • sub <rn>, <rs | value>
  • and <rn>, <rs>
  • or <rn>, <rs>
  • xor <rn>, <rs>
  • not <rn>
  • b <value>
  • mov <rn>, <rs | value>
  • load <rn>, [<rs>]
  • sto <rs | value>, [<rn>]
  • test <rn>, <rs>
  • stop

arrangement:

  1. top left: clock in
  2. middle left: data in
  3. bottom left: input enable
  4. top right: address out
  5. middle right: data out
  6. bottom right: output enable

connecting to pixy:

  • pick a device you'll be using to store programs and data, i.e. RAM.
  • link data in to RAM's data output through a tristate.
  • link data out to RAM's data input through a tristate.
  • link address out to RAM's address input.
  • link clock in to an oscillator. 
  • link input and output enables to the tristates.

when the clock starts, the processor will try to execute any instructions found at address 0x0000.


internals:

  • the CU uses microcode stored in an EEPROM to implement the instruction set.
  • information is transferred between components using a data bus which is wrapped around the circuit.
  • programs can access four general purpose registers and RAM. They can also talk to any peripherals connected via memory mapping.
  • a FIN signal is used to mark the end of an instruction and save clock cycles.
  • conditional instructions work by triggering FIN (or not) based on ALU flags.

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t729 is a 6/12-trit balanced ternary processor.

It is built with normal binary logic gates using binary encoded ternary (10, 00, 01) to create the ternary logic gates. While this probably increases complexity, I've not found a logic simulator that does ternary. I tried circuit simulators but working with negative and positive voltages with transistors is kind of a pain and very slow to design. Sure binary encoded ternary is more wire complex but it does only require one voltage and should technically use less power and run faster. Also binary logic gates are super cheap. Using binary logic gates also means the design should work on FPGAs and could in theory get manufactured as a microprocessor.

I've gone with 6-trit = 1 Tryte for my system. 12-trit / 2 Tryte is a "word".

Data and instruction width is 6-trit (729)
Address width is 12-trit (531,441)

The t729 is a hobby project I've been extremely slowly working on for a few years. It's purely a project for fun. Completely self taught so probably a lot of doing things the wrong way.

Currently I'm mostly hung up on instruction set. It's hard choosing which instructions to have and how to implement them.

Huge thanks to http://homepage.divms.uiowa.edu/~jones/ternary/ for the ternary logic knowledge.

If you would like to add something to the project or point something out please comment or e-mail (gmail*dyne.unlimited)


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Implementation of the processor MIPS R2000 in it's unicycle version.


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An 8-bit CPU with an instruction set that includes the analytic integration and differentiation of polynomial expressions.


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This module implemets the Register File of a basic version of RISC-V processor.


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Procesorul8