{"id":1317593,"name":"ALU_3Bits","author_id":242004,"forked_project_id":null,"project_access_type":"Public","created_at":"2024-05-26T12:28:31.375Z","updated_at":"2024-05-26T15:04:05.297Z","assignment_id":null,"project_submission":false,"image_preview":{"url":"/uploads/project/image_preview/1317593/preview_17167358452892246.jpeg"},"description":"

This is a replication of an ALU (Arithmetic and Logical Unit) containing a Full Adder, logical gates to invert both inputs separately, to make both inputs zero separately, to invert the output, to add both inputs or to get the logical result of AND (X, Y).

Instructions on how to use:
Double click on the main 3 bit inputs to set their value individually. Beware that any input of less or more than 3 bits will make the ALU malfunction. Also only input binary values. Inputs are signed in the 'Two's complement' method.
Click once on the control values to set them alternatively on '0' or '1'.
Outputs are read-only.

Values:
Input values are X and Y. They are 3 bits inputs.
Control values are ZX, NX, ZY, NY, F and NO. They are 1 bit inputs.
ZX = 1 means X input is '000', otherwise it is simply X.
NX = 1 means X input gets inverted (NOT(X)), otherwise it is simply X. This inverter happens after X has (or not) been set to zero.
ZY = 1 means Y input is '000', otherwise it is simply Y.
NX = 1 means Y input gets inverted (NOT(Y)), otherwise it is simply Y. This inverter happens after Y has (or not) been set to zero.
F = 1 means the full adder is selected for the ouput, otherwise the AND (X, Y) method is selected.
NO = 1 means the ouput will be inverted (NOT(OUT)), otherwise it is simply OUT. This happens after either the full adder or the AND logical gate.
Used gates are NOT, AND, OR, MUX.
Ouput is in three bits.
Flag outputs are ZR and NG.
ZR = 1 means the output is '000', otherwise it is any other combination of 3 bits
NG = 1 means the output is negative ('1xx'), otherwise it is positive ('0xx').
A light green line means the value it carries is '1', dark green means '0'.
Intermediate carries of added bits have been output in the circuit for a better understanding of how it works and are labeled R0, R1, R2 and R3

Possible circuits are:
ADD(X, Y)
ADD(NOT(X), Y)
ADD(X, NOT(Y))
ADD(NOT(X), NOT(Y))
ADD(0, Y)
ADD(X, 0)
ADD(0, 0)
ADD(NOT(0), Y)
ADD(NOT(X), 0)
ADD(NOT(0), 0)
ADD(0, NOT(Y))
ADD(X, NOT(0))
ADD(0, NOT(0))
ADD(NOT(0), NOT(Y))
ADD(NOT(X), NOT(0))
ADD(NOT(0), NOT(0))

AND(X, Y)
AND(NOT(X), Y)
AND(X, NOT(Y))
AND(NOT(X), NOT(Y))
AND(NOT(0), Y)
AND(NOT(X), 0)
AND(NOT(0), 0)
AND(0, NOT(Y))
AND(X, NOT(0))
AND(0, NOT(0))
AND(NOT(0), NOT(Y))
AND(NOT(X), NOT(0))
AND(NOT(0), NOT(0))

NOT(ADD(X, Y))
NOT(ADD(NOT(X), Y))
NOT(ADD(X, NOT(Y)))
NOT(ADD(NOT(X), NOT(Y)))
NOT(ADD(0, Y))
NOT(ADD(X, 0))
NOT(ADD(0, 0))
NOT(ADD(NOT(0), Y))
NOT(ADD(NOT(X), 0))
NOT(ADD(NOT(0), 0))
NOT(ADD(0, NOT(Y)))
NOT(ADD(X, NOT(0)))
NOT(ADD(0, NOT(0)))
NOT(ADD(NOT(0), NOT(Y)))
NOT(ADD(NOT(X), NOT(0)))
NOT(ADD(NOT(0), NOT(0)))

NOT(AND(X, Y))
NOT(AND(NOT(X), Y))
NOT(AND(X, NOT(Y)))
NOT(AND(NOT(X), NOT(Y)))
NOT(AND(NOT(0), Y))
NOT(AND(NOT(X), 0))
NOT(AND(NOT(0), 0))
NOT(AND(0, NOT(Y)))
NOT(AND(X, NOT(0)))
NOT(AND(0, NOT(0)))
NOT(AND(NOT(0), NOT(Y)))
NOT(AND(NOT(X), NOT(0)))
NOT(AND(NOT(0), NOT(0)))

","view":15,"slug":"alu_3bits","searchable":"'0':106,324,372,376,378,379,382,387,390,391,393,399,401,403,406,413,416,418,437,442,445,446,448,454,456,458,461,468,471,473,496,501,504,505,509,515,519,520,523,530,533,535,539,547,551,553,577,583,587,588,591,598,601,603,607,615,619,621 '000':147,185,287 '0xx':309 '1':108,138,142,154,180,192,218,237,282,298,320 '1xx':304 '3':57,74,123,295 '3bits':623 'ad':328 'add':34,355,358,362,366,371,374,377,380,384,388,392,396,400,404,409,414,475,479,484,489,495,499,503,507,512,517,522,527,532,537,543,549 'adder':15,222,257 'also':81 'altern':104 'alu':7,79,622 'arithmet':8 'better':338 'bewar':65 'binari':84 'bit':58,75,124,139,274,296,329 'carri':318,326 'circuit':335,353 'click':53,95 'combin':293 'complement':93 'contain':12 'control':99,126 'dark':321 'doubl':52 'either':254 'f':133,217 'flag':275 'full':14,221,256 'gate':17,262,264 'get':39,158,196 'green':312,322 'happen':169,207,252 'individu':64 'input':21,26,36,59,68,83,86,115,125,140,145,157,183,195 'instruct':47 'intermedi':325 'invert':19,30,159,168,197,206,243 'label':346 'less':70 'light':311 'line':313 'logic':10,16,41,261 'main':56 'make':24,77 'malfunct':80 'mean':143,155,181,193,219,238,283,299,314,323 'method':94,233 'mux':269 'negat':303 'ng':280,297 'nx':130,153,191 'ny':132 'otherwis':148,162,186,200,228,246,288,305 'ouput':227,240,270 'output':32,109,276,285,301,332 'posit':308 'possibl':352 'r0':347 'r1':348 'r2':349 'r3':351 'read':112 'read-on':111 'replic':4 'result':42 'select':224,235 'separ':22,28 'set':61,102,176,214 'sign':88 'simpli':151,165,189,203,249 'three':273 'two':91 'understand':339 'unit':11 'use':51,263 'valu':63,85,100,114,116,127,316 'work':343 'x':45,118,144,152,156,161,166,171,231,356,360,363,368,375,386,397,411,420,424,427,432,441,452,466,476,481,485,491,500,514,528,545,556,561,565,571,582,596,613 'y':46,120,182,190,194,199,204,209,232,357,361,365,370,373,383,395,408,421,425,429,434,438,450,463,477,482,487,493,497,510,525,541,557,562,567,573,578,593,609 'zero':27,178,216 'zr':278,281 'zx':129,141 'zy':131,179","lis_result_sourced_id":null}

Samuel Muylaert

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