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This is an example implementation of the uCISC instruction set as defined at https://github.com/grokthis/ucisc. So far it implements the Copy and ALU instructions. Note that multiplication, division and floating point ALU operations are not currently supported. This processor is enough to execute real programs.

The EEPROM is programmed with the fibonacci calculation found in the uCISC examples.

[ Under Development ]

This is a 16-bit processor with 18 instructions of length 16 bit, 16 registers of size 16 bit and only the primary cache in its architecture.

[ Instruction Set ]

from 0 to f
0 is also known as ra as its used for jump and link and jump register

instructions

0000 0XXX XXXX XXXX    - no-op     X can be anything- no operation
0000 1XXX XXXX XXXX    - jmp   X is the address offset from pc  - jump
0001  XXXX YYYY YYYY    - lli   X is the register to write data to and Y is the data to load in lower 8 bits- load lower imediate
0010  XXXX YYYY YYYY    - orui  X is the register to write data to and Y is the data to or with the upper 8 bits in X - or upper imediate
0011  0XXX XXXX XXXX    - jal   X is the address offset to pc and pc+1 is stored in ra - jump and link
0011  1XXX  XXXX XXXX    - jr   X can be anything, pc is restored by value in ra- jump register( only from ra register )
0100 XXXX YYYY ZZZZ    - shw  X is the register containing the data to write, Y is the offset, Z is the register containing the address in memory  - store 16bits in memory ( Addresses in memory can be read or written 16 bits at a time only)
0101  XXXX YYYY ZZZZ   - lhw  X is the register to store data in, Y is the offset,  Z is the register containing the memory address  - load 16bits from memory                          ( That is 0 represents first 16 bits and 1 represents next 16 bits)
0110  XXXX YYYY ZZZZ    - beq  X is the PC offset, Y and Z are registers to compare - break equal
0111  XXXX YYYY ZZZZ   - bne   X is the PC offset, Y and Z are registers to compare - break not equal

In the following, assume $ is the operation

X, Y and Z are registers, X=Y$Z

1000 XXXX YYYY ZZZZ    - and   - and gate
1001 XXXX YYYY ZZZZ    - or    - or gate
1010 XXXX YYYY ZZZZ    - add   - addition
1100 XXXX YYYY ZZZZ    - and~  - A and ~B
1101  XXXX YYYY ZZZZ   - or~   - A or ~B
1110  XXXX YYYY ZZZZ    - sub   - subtraction

if(Y<Z) X=1 else X=0

1111  XXXX YYYY ZZZZ    - stl   - set less than

To do list:

Forwarding unit - on going

Hazard detection unit - yet to start

Update! I managed to un-corrupt it and finish the project! You can find the finished branch here as part of the 256-Series:
https://circuitverse.org/users/4699/projects/256-series

After nearly making it work, and getting my Flappy Bird code quite far, the project corrupted, so currently it does not work anymore. Please look at other Femto-4 forks to see where the project was. 

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Test code demonstrating basic functionality. First it uses most instructions to ensure they work, before showing the graphical capabilities of the computer.

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
15x15 pixel display

Will have:
An ALU capable of shift right and multiplying
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number register
Text outputs
Stack
Assembler (hopefully)
Save memory
Several pre-written carts to play with

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with. 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space, including many special registers like the program counter and the Memory Address Register. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there is only one cart). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc (subject to change). This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the least significant bit of the mode register is low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high too by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. Setting the second bit of the mode register will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. A value of 8 works consistently, though I have not toyed with values much higher. In future, additional execution options will likely be made available, the current planned ones being enabling falling edge execution as well as rising edge execution, to double the execution speed, updating graphics on both edges of the clock pulse, updating graphics every other clock pulse, updating graphics when the update graphics command is run, and disabling graphics. 

Graphics:
The Femto-4 is capable of driving a 15x15 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. Should a falling edge "fast execution" mode be added and work, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. The demonstration code uses two "sprites". The first "sprite" is the black background, and the second "sprite" is the red rectangle. The coordinate value of the red rectangle is incremented every frame, causing the animation. Had I had more storage I might have incremented the colour as well to show the colour capabilities of the Femto-4. Whilst driving a larger screen might be nice, given the limit in the number of instructions per second, it is unlikely that it could be well utilised, which is why I have chosen this screen size. A variation with larger screens may appear at some point, but this is a low priority for me. 

ALU:
The basic ALU (currently the only implemented bit of the ALU) was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift right, adding and subtracting. This is unlike my previous computer which had different chips for each operation it could do. Additional capability chips, such as multiplication and shifting right will be added later. 

General Registers:
This computer probably has more general registers than it should. What makes the 256 general registers unique is that they can be easily piped into the A and B operators when performing ALU operations. This allows ALU instructions to only have one operand, with the lower 8-bits being the register address of value A, and with the higher 8-bits being the register address of value B. 

Timing:
This computer is timed using a several standard delay chips. The pulse length running in to the computer is about 10k units long. This then runs into the pulse generator which pulses 32 unique lines with a 20k delay between them which can then be used to time when control lines pulse. This is bundled together into a 32-bit timing bus, which then uses bit selectors to select how much delay that pulse will have. This is why there are 32 sub-circuits which are effectively just bit specific bit selectors - they allow me to "compactly" build timing circuitry. In addition to the main delay of 20k between the chosen bits, I can add "on-delays" to further delay the control line, allowing me to ensure that control lines like the enable read line can be on before the register reads from them. "On-delays" were first constructed to ensure that the data out line did not have contention issues - it ensured that the previous address outputting data was disabled before the next address outputting data onto the line was enabled. They add 1k of delay on the rising edge, and less than 10 delay on the falling edge. This way I do not need to worry about "on-delays" increasing the delay of one command into the next. The "Fast Execution" loop gives a pulse of 300k, with a delay between pulses of around 600k. This ensures that the previous instruction will finish before the next instruction starts. I do not entirely understand how the timing system works, since the in my mind it should be producing contention issues, however proofing it against that breaks the system entirely. 

Other Notes:
You may note that I use 32b EEPROM banks instead of 16b ones. This choice was made to reduce the number of EEPROM banks required. Each half of the EEPROM's 32b output is treated as one address. Whilst this added a slight bit of additional complexity in writing, it halved the number of EEPROM banks required. This project was started when I realised that EEPROM banks could be that large, since a major sticking point in a previous attempt was the number of EEPROM banks required. (That attempt is private and completely dysfunctional. It also suffers from contention errors caused by incomplete splitters.)

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Test "Hello World" code demonstrating text input and output functionality of the computer. Once the computer has outputted "Hello World! Type something!" it will shift in any input from the keyboard into the text output.

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
15x15 pixel display

Updates:
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number register
Text outputs

Will have:
An ALU capable of shift right and multiplying
Stack
Assembler (hopefully)
Save memory
Several pre-written carts to play with
Maybe separate GPU to help with graphics handling

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with. 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space, including many special registers like the program counter and the Memory Address Register. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there is only one cart). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc (subject to change). This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the least significant bit of the mode register is low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high too by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. A value of hex 10 (16) is the highest value I have found to work. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. This raises the max execution speed to 640 instructions per second. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for rising edge only (normal speed), 01 for duel edge (double speed), 10 for every other clock pulse (half speed), and 11 for when given the correct OP Code (controlled updates). The OP Code used for the graphics update is (01). The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics.

Graphics:
The Femto-4 is capable of driving a 15x15 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. Should a falling edge "fast execution" mode be added and work, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. The demonstration code uses two "sprites". The first "sprite" is the black background, and the second "sprite" is the red rectangle. The coordinate value of the red rectangle is incremented every frame, causing the animation. Had I had more storage I might have incremented the colour as well to show the colour capabilities of the Femto-4. Whilst driving a larger screen might be nice, given the limit in the number of instructions per second, it is unlikely that it could be well utilised, which is why I have chosen this screen size. A variation with larger screens may appear at some point, but this is a low priority for me. 

ALU:
The basic ALU (currently the only implemented bit of the ALU) was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift right, adding and subtracting. This is unlike my previous computer which had different chips for each operation it could do. Additional capability chips, such as multiplication and shifting right will be added later. 

General Registers:
This computer probably has more general registers than it should. What makes the 256 general registers unique is that they can be easily piped into the A and B operators when performing ALU operations. This allows ALU instructions to only have one operand, with the lower 8-bits being the register address of value A, and with the higher 8-bits being the register address of value B. 

Timing:
This computer is timed using a several standard delay chips. The pulse length running in to the computer is about 10k units long. This then runs into the pulse generator which pulses 32 unique lines with a 20k delay between them which can then be used to time when control lines pulse. This is bundled together into a 32-bit timing bus, which then uses bit selectors to select how much delay that pulse will have. This is why there are 32 sub-circuits which are effectively just bit specific bit selectors - they allow me to "compactly" build timing circuitry. In addition to the main delay of 20k between the chosen bits, I can add "on-delays" to further delay the control line, allowing me to ensure that control lines like the enable read line can be on before the register reads from them. "On-delays" were first constructed to ensure that the data out line did not have contention issues - it ensured that the previous address outputting data was disabled before the next address outputting data onto the line was enabled. They add 1k of delay on the rising edge, and less than 10 delay on the falling edge. This way I do not need to worry about "on-delays" increasing the delay of one command into the next. The "Fast Execution" loop gives a pulse of 300k, with a delay between pulses of around 600k. This ensures that the previous instruction will finish before the next instruction starts. I do not entirely understand how the timing system works, since the in my mind it should be producing contention issues, however proofing it against that breaks the system entirely. 

Other Notes:
You may note that I use 32b EEPROM banks instead of 16b ones. This choice was made to reduce the number of EEPROM banks required. Each half of the EEPROM's 32b output is treated as one address. Whilst this added a slight bit of additional complexity in writing, it halved the number of EEPROM banks required. This project was started when I realised that EEPROM banks could be that large, since a major sticking point in a previous attempt was the number of EEPROM banks required. (That attempt is private and completely dysfunctional. It also suffers from contention errors caused by incomplete splitters.) The memory wrappers allow external chips to interact with the main dat control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Outputs the twelve days of Christmas into the text output. 

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
15x15 pixel display

Updates:
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number register
Text outputs

Will have:
An ALU capable of shift right and multiplying
Stack
Assembler (hopefully)
Save memory
Several pre-written carts to play with
Maybe separate GPU to help with graphics handling

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with. 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space, including many special registers like the program counter and the Memory Address Register. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there is only one cart). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc (subject to change). This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the least significant bit of the mode register is low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high too by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. A value of hex 10 (16) is the highest value I have found to work. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. This raises the max execution speed to 640 instructions per second. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for rising edge only (normal speed), 01 for duel edge (double speed), 10 for every other clock pulse (half speed), and 11 for when given the correct OP Code (controlled updates). The OP Code used for the graphics update is (01). The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics.

Graphics:
The Femto-4 is capable of driving a 15x15 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. Should a falling edge "fast execution" mode be added and work, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. The demonstration code uses two "sprites". The first "sprite" is the black background, and the second "sprite" is the red rectangle. The coordinate value of the red rectangle is incremented every frame, causing the animation. Had I had more storage I might have incremented the colour as well to show the colour capabilities of the Femto-4. Whilst driving a larger screen might be nice, given the limit in the number of instructions per second, it is unlikely that it could be well utilised, which is why I have chosen this screen size. A variation with larger screens may appear at some point, but this is a low priority for me. 

ALU:
The basic ALU (currently the only implemented bit of the ALU) was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift right, adding and subtracting. This is unlike my previous computer which had different chips for each operation it could do. Additional capability chips, such as multiplication and shifting right will be added later. 

General Registers:
This computer probably has more general registers than it should. What makes the 256 general registers unique is that they can be easily piped into the A and B operators when performing ALU operations. This allows ALU instructions to only have one operand, with the lower 8-bits being the register address of value A, and with the higher 8-bits being the register address of value B. 

Timing:
This computer is timed using a several standard delay chips. The pulse length running in to the computer is about 10k units long. This then runs into the pulse generator which pulses 32 unique lines with a 20k delay between them which can then be used to time when control lines pulse. This is bundled together into a 32-bit timing bus, which then uses bit selectors to select how much delay that pulse will have. This is why there are 32 sub-circuits which are effectively just bit specific bit selectors - they allow me to "compactly" build timing circuitry. In addition to the main delay of 20k between the chosen bits, I can add "on-delays" to further delay the control line, allowing me to ensure that control lines like the enable read line can be on before the register reads from them. "On-delays" were first constructed to ensure that the data out line did not have contention issues - it ensured that the previous address outputting data was disabled before the next address outputting data onto the line was enabled. They add 1k of delay on the rising edge, and less than 10 delay on the falling edge. This way I do not need to worry about "on-delays" increasing the delay of one command into the next. The "Fast Execution" loop gives a pulse of 300k, with a delay between pulses of around 600k. This ensures that the previous instruction will finish before the next instruction starts. I do not entirely understand how the timing system works, since the in my mind it should be producing contention issues, however proofing it against that breaks the system entirely. 

Other Notes:
You may note that I use 32b EEPROM banks instead of 16b ones. This choice was made to reduce the number of EEPROM banks required. Each half of the EEPROM's 32b output is treated as one address. Whilst this added a slight bit of additional complexity in writing, it halved the number of EEPROM banks required. This project was started when I realised that EEPROM banks could be that large, since a major sticking point in a previous attempt was the number of EEPROM banks required. (That attempt is private and completely dysfunctional. It also suffers from contention errors caused by incomplete splitters.) The memory wrappers allow external chips to interact with the main dat control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 

Observing someone else's design! Not mine! Just seeing how they designed their system.

The original: 
https://circuitverse.org/users/17603/projects/16-bit-computer-be083c00-104f-4bec-bfea-0cdc0126e9bc

Things I've added (only two things):

1) I fixed the single pixel GPU contention issue (not the GPU RAM reset issue)
2) I implemented my "fast execution" system in it (see a later version of the Femto-4 to see its origins, or see the Delay Introduction for its explanation)
This computer is far less intensive than my design in terms of simulation load, and can execute 256 instructions per clock cycle as opposed to the Femto-4's measly ~16. (Admittedly the Femto-4 does do more per instruction but not 11 times more. Also I suspect the Femto-4's graphics updates are partly to blame for this). This raises the execution speed from 10 instructions per second to 2560 instructions per second. It is so fast that it can run through all 65536 instructions the computer can store in 25.6 seconds. When running the Hello World Program it runs through the entire 84 line code 3 times, and then executes 4 more instructions, making it appear to only execute 4 instructions at a time.

Note that the execution speed could be doubled by using both edges of the clock to pulse the loop, increasing the instructions per second to 5120, making it actually capable of running decent programs. With this it probably would be feasible to drive decently fast graphics. 

Delay Introduction:
https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction

Latest Femto-4 Update:
https://circuitverse.org/users/4699/projects/femto-4v1-3-computer

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Cart A: Flappy Bird
Cart B: Some Pixel Art
Cart C: Screensaver

Assembler:
https://repl.it/@Sanderokianstfe/Femto-4-Assembler#DeveloperGuide.txt

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks, allowing for a standard Cart to hold up to 512kx16b of data
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
16x16 pixel display
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number generator
Text outputs
An ALU capable of shift right, multiplying, dividing, and other specialised functions
Stack
Assembler (written in an external program)
Save memory
Two pre-written carts to play with
Fixed code controlled graphics updates
Made Bootloader clear TTY, Keyboard, and Controller Pushed
Fixed Register ALU instructions
Updated Cart A and Cart B to make use of the Register ALU instructions

Updates:
Another pre-written cart to play with
Updated the sprite-art cart to respond to the start button on both controllers. 

Will have:
More pre-written carts
Bug fixes

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note:
The Flappy Bird high score is mine. If you want to save your own scores permanently you will have to fork it. 

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with (and there are a lot of ALU processes). 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there are currently only two carts). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers, the, stack, inputs, outputs, and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high to by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0x0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. It is also paused by the OP Code 0x0001. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for falling edge only (normal speed), 01 for dual edge (double speed), 10 for every other clock pulse (half speed), and 11 for code controlled, where the 0x0001 OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. 

Graphics:
The Femto-4 is capable of driving a 16x16 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. When using dual-edge "Faster Execution", the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. 

ALU:
The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting. This is unlike my previous computer which had different chips for each operation it could do. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the Femto-4's graphics data. 

Conditional Jumps:
The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. 
The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. In theory a similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not.
The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing:
This computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. For more information see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction. 

Other Notes:
The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 

This is a secret to everybody, unless you found it. 

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a fork from the main branch to keep a semi-functional version around. This project was started around November 2020.

Currently runs:
Cart A: Flappy Bird
Cart B: Some Pixel Art

Assembler:
https://repl.it/@Sanderokianstfe/Femto-4-Assembler#DeveloperGuide.txt

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks, allowing for a standard Cart to hold up to 512kx16b of data
An ALU capable of logical operators, addition, subtraction and shift left
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
16x16 pixel display
Inputs, both "controllers" and keyboards
"Faster Execution" - Runs instructions on both edges of the clock pulse 
Random number generator
Text outputs
An ALU capable of shift right, multiplying, dividing, and other specialised functions
Stack
Assembler (written in an external program)
Save memory
One pre-written cart to play with

Updates:
Another pre-written cart
Fixed code controlled graphics updates
Made Bootloader clear TTY, Keyboard, and Controller Pushed
Fixed Register ALU instructions
Updated Cart A and Cart B to make use of the Register ALU instructions

Will have:
More pre-written carts
Bug fixes

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note:
The Flappy Bird high score is mine. If you want to save your own scores permanently you will have to fork it. 

General Architecture:
The Femto-4 has variable length instructions that are comprised of multiple 16-bit chunks. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neuman architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with (and there are a lot of ALU processes). 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. (However, currently there are currently only two carts). The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers, the, stack, inputs, outputs, and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 50ms, or 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high to by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0x0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. It is also paused by the OP Code 0x0001. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for falling edge only (normal speed), 01 for dual edge (double speed), 10 for every other clock pulse (half speed), and 11 for code controlled, where the 0x0001 OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. 

Graphics:
The Femto-4 is capable of driving a 16x16 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. Currently, every time the clock pulses low, the screen is refreshed. When using dual-edge "Faster Execution", the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed. The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically increase the simulation's stack usage. 

ALU:
The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting. This is unlike my previous computer which had different chips for each operation it could do. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the Femto-4's graphics data. 

Conditional Jumps:
The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. 
The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. In theory a similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not.
The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing:
This computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. For more information see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction. 

Other Notes:
The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 

This is a secret to everybody, unless you found it. 

A 16-bit computer/maybe console inspired thing, the Femto-4. This will be the main branch and backups will be forks from it. This project was started around November 2020.

Currently runs: 

• Cart A: Flappy Bird 
• Cart B: Some Pixel Art 
• Cart C: Screensaver 
• Cart D: Snake 
• Cart E: Phemton Demonstrations 
• Cart F: Competitive Snake 
• Cart G: Tic Tac Toe 
• Cart H: Connect 4 
• Cart I: NIM
• Cart J: Bad Apple
• Bundle Cart: All carts in one 
• Cart 2A: 32x32 Snake
• Cart 2B: 32x32 Competitive Snake
• Cart 2C: 32x32 Pixel Art
• Cart 2D: 32x32 Bad Apple
• Bundle Cart 2: All 32x32 carts in one 

Assembler: 

• https://github.com/Comerstar/PhemtonCompiler/blob/main/Assembler/DeveloperGuide.txt

Compiler: 

• https://github.com/Comerstar/PhemtonCompiler/blob/main/PhemtonLiteCompiler/PhemtonDeveloperGuide.txt

The 256-Series: 

• https://circuitverse.org/users/4699/projects/256-series

Full screen Notes:

For some reason, the Femto-4v2.6 only is having issues around caching previous subcircuits. Should you need to use something to unbind key entries from the full screen button, toggle the clock. Previous versions are completely unaffected. 

Cart Notes: 

Cart A: 

• The first cart written for the Femto-4. 

Cart B: 

• The sprites in the cart are: 
• A: Femto-4 Logo. 
• B: Madeline from Celeste. 
• C: Madeline from Celeste (again). 
• D: Part of you aka Badeline from Celeste. 
• E: A strawberry from Celeste.
• F: Standing Mario from Super Mario Bros. 
• G: Jumping Mario from Super Mario Bros. 
• H: Standing Mario from Super Mario Bros 3. 
• I: Running Mario from Super Mario Bros 3. 
• J: Sanderokian (my own character). 

Cart C: 

• Enter anything into the keyboard to randomise the colours. 
• Enter r into the keyboard to reset the colours. 

Cart D: 

• WASD Pad is recommended. 
• Game settings (enter the letter before starting the game to use the setting): 
• e: toggle whether crashing into the edges results in a game over. 
• The two modes (with/without edge collisions) have two separate high scores. 
• w: change the snake's colour scheme to white. 
• r: change the snake's colour scheme to red. 
• y: change the snake's colour scheme to yellow. 
• o: change the snake's colour scheme to orange. 
• p: change the snake's colour scheme to purple. 
• a: change the snake's colour scheme to aqua. 
• g: change the snake's colour scheme to green. 
• b: change the snake's colour scheme to blue. 
• m: change the snake's colour scheme to magenta. 
• 1: change the snake's colour scheme to pink. 
• 2: change the snake's colour scheme to light blue. 
• 3: change the snake's colour scheme to the challenge colour scheme with an invisible body. 
• 0: randomise the snake's colour scheme. 

Cart E: 

• The test codes in the cart are: 
• 1: Hello World. 
• 2: Single Operator Calculator. 
• 3: Exponentiation Calculator. 
• 4: Fibonacci Calculator. 
• 5: Keyboard to TTY Test. 
• 6: Keyboard to TTY LDI LID Test. 
• 7: Keyboard to TTY LII Test. 
• 8: Keyboard to TTY LIA Test. 

Cart F: 

• WASD Pad is essentially required. 
• Game settings (enter the letter before starting the game to use the setting): 
• e: toggle whether crashing into the edges results in a game over. 
• w: toggle whether the number of wins each player has is tracked. 
• s: toggle whether the total score each player has scored is tracked. 
• d: display the total wins and total scored. 
• r: reset the tracked statistics. 

Cart G: 

• The small light in the corner indicates which player's turn it is. 
• When it is dimmed, it means that the computer is processing that player's turn. 
• Game settings (enter the letter before starting the game to use the setting): 
• w: toggle whether the number of wins each player has is tracked. 
• s: toggle automatic start player swapping. d: display the wins each player has. 
• r: reset the wins each player has. 

Cart H: 

• The bar at the top indicates which player's turn it is. 
• When it is dimmed, it means that the computer is processing that player's turn. 
• Game settings (enter the letter before starting the game to use the setting): 
• w: toggle whether the number of wins each player has is tracked. 
• s: toggle automatic start player swapping. 
• d: display the wins each player has. 
• r: reset the wins each player has.

Cart I:

• Game settings (enter the letter before starting the game to use the setting):
• w: toggle whether the number of wins each player has is tracked. 
• s: toggle automatic start player swapping. 
• d: display the wins each player has. 
• r: reset the wins each player has. 
• i: display the game instructions. 
• c: toggle the whether player 2 is played by the computer. 

Cart J:

• Plays Bad Apple
• There are no further controls

Cart 2A:

• The options are the same as Cart D. 

Cart 2B:

• The options are the same as Cart F. 

Cart 2C:

• The sprites in the cart are: 
• A: Femto-4 Logo. 
• B: Sanderokian (my own character). 
• C: Alstran (my own character). 

Cart 2D:

• Plays Bad Apple on the larger screen
• There are no further controls

Features: 

• Immediate, direct, & indirect memory access. 
• Jumps & conditional jumps. 
• 16-bit address space. 
• Switchable memory banks, allowing for a standard cart to hold up to 1MB of data. 
• An ALU capable of logical operators, addition, subtraction, shift left, shift right, multiplying, dividing, & other specialised functions. 
• Fast execution - can run more than one instruction per clock cycle. 
• 16x16 pixel display with 32 sprites and 15-bit direct colour. 
• 32x32 pixel display with 32 sprites which can have up to 18-bit direct colour. 
• Two controllers, a keyboard mapping for the controllers, & a keyboard for text inputs. 
• RNG, TTY, stack, & save memory. 
• Von Neumann Architecture. 
• Assembler & compiler (written in Python). 
• Twelve pre-written carts to play with. 

Updates: 

v1.0: 

• Finished the project and added Cart A. 

v1.1: 

• Added Cart B, some Pixel Art. 
• Fixed GRF, & AXR instructions. 
• Made Bootloader clear TTY, Keyboard, & Controller Pushed. 
• Updated Cart A & Cart B to make use of AXR instructions. 

v1.2: 

• Added Cart C, a Screensaver. 
• Updated Cart B to respond to the start button on both controllers. 

v1.3: 

• Added Cart D, Snake. 
• Moved to new project to fix issues around searching for projects branched from private projects. 
• Removed unnecessary EEPROM banks and write lines from all carts. 
• Made Reset clear WRAM and the General Registers. 

v1.4: 

• Fixed Keyboard. 
• Added a Bundle Cart that allows you to view all the carts without changing carts (you must reset the console to view another cart). 
• Fixed bug in the standard bank design which wrote data to incorrect addresses. 
• Fixed contention issue in Mult. 
• Added Annotations to the In Debug. 

v1.5: 

• Added Snake Player. 
• Added Reset & Power labels to the relevant buttons. 

v2.0: 

• Further optimisation to reduce lag/increase execution speed. 
• Added more memory access options. 

v2.1: 

• Further optimisation of the CU. 
• Added a keyboard to controller mapping. 

v2.2: 

• Continued optimisation and overhaul of the CU. 
• Removed old CU & compare circuits. 
• Added additional stack access instructions. 
• Updated the debug versions with the changes, as well as fixing bugs in the debug versions. 
• Designed a Logo for the Femto-4. 
• Rewrote Cart C to allow the sprites to be viewed in any order, and added the logo to it. 

v2.3: 

• Introducing Phemton Lite, the first version of the Femto-4's high level languages. 
• Added a link to Phemton Lite's compiler. 
• Added Cart E to demonstrate code written in Phemton Lite. 
• Combined SpecialD & ROMD1, and removed SpecialD & ROMDB. 
• Updated Snake code & Bundle code to match the new addresses. 
• Added Cart F, a competitive version of Snake. 
• Added an additional sprite into Cart B. 
• Fixed issues with LII, LXA & LXP instructions. 

v2.4: 

• Fixed alignment of the upper carts. 
• Added Cart G & Cart H, Tic Tac Toe & Connect 4 written in Phemton Lite. 
• Added progress lights to Cart G & Cart H. 
• Reworked bundle cart to make the code shorter and more efficient for large numbers of carts. 
• Made Cart G & Cart H faster. 
• Reshuffled Cart E test codes and added 2 Cart E test codes, exponentiation & Fibonacci calculation. 
• Added game options to Cart D, Cart F, Cart G, & Cart H. 
• Updated Cart C to allow the colours to be randomised. 
• Added optional colour schemes for Cart D. 
• Fixed Snake Player. 
• Remade the multiply and divide circuits to take advantage of the inbuilt adders. 
• Removed old MultM and DivM circuits. 

v2.5: 

• Further optimisation of the CU. 
• Optimisation of the fast execution clocks for the computer, the graphics, & the WASD Pad. 
• Fixed debug versions' issues with Phemton conditionals and added optimisations to the debug versions. 
• Added 32x32 screen PPU. 
• Added Cart 2A, Cart 2B, & Cart 2C, 32x32 versions of Snake, Competitive Snake, & Pixel Art. 
• Added Cart I, NIM written in Phemton Lite. 

v2.6

• Added the ability to directly write sprites to the PPU during execution.
• Significantly optimised the CU by removing unnecessary subcircuits.
• Introduced significant quantities of lazy evaluation to further improve performance.
• Added Cart J, and Cart 2D, which both play Bad Apple.
• The Femto-4 can now be added to the set of things that plays Bad Apple.

Future Updates: 

• More pre-written carts. 
• Bug fixes. 
• Adding an optimiser to the compiler. 
• Phemton Full. 
• Phemton Plus. 

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note: The Flappy Bird high score and the Snake high score are mine. If you want to save your own scores permanently you will have to fork the project. 

The Femto-4

General Architecture: The Femto-4 is a 16-bit, Von Neumann architecture computer with variable length instructions that are comprised of multiple 16-bit words. It has many features associated with CISCs, such as variable length instructions, and multicycle indirect loads, however operates like a RISC, with each instruction taking exactly 1 clock cycle. This was done to give the Femto-4 power whilst keeping its construction simple. First the OP code of the instruction is read, and then depending on the OP code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP code space is so empty that the data will likely be passed one at a time until the next valid instruction. Instructions are read from main memory, making this architecture a Von Neumann architecture as opposed to a Harvard architecture. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to most special registers during the instruction. OP codes and operands are all 16-bits. The large OP code size was chosen due to the high number of ALU instructions. There are approximately 500 interpretable OP codes that the computer can handle. 

Memory Mapping: The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 0b01, 0b10, or 0b11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 0x00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed WRAM chip that cannot be switched out, the bootloader, the PPU data, general registers, the stack, inputs, outputs, and a few special registers, such as the protect, mode, and flag registers. 

Fast Execution: Execution at the fastest clock speed (one pulse every 100ms, or 10Hz, which is defined as the clock changing state every 50ms, or at a rate of 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 0x00ca, the mode register, and address 0x00cb, the protect register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When bit 0 is set high, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping an inverter into itself, producing a loop that will pulse indefinitely until the looping line is stopped by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. Fast execution is always paused by a 0x0000 and 0x0001 OP Code. Bit 2 enables falling edge fast execution, which can be done with rising edge fast execution producing dual edge fast execution. Setting the third bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protect register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 0b00 for falling edge only (normal speed), 0b01 for dual edge (double speed), 0b10 for every other clock pulse (half speed), and 0b11 for code controlled, where the 0x0001OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics, reducing lag by prevent the graphics fast execution loop from running. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. By default, the Femto-4 executes with a protection value of 16, to allow the carts to run smoothly, however, depending on the instructions being used, that number can be raised to 64. 

Graphics (16x16): The Femto-4 is capable of driving a 16x16 15-bit direct colour screen. It has space for 32 sprites which are rectangles with an assigned colour. All the sprites are drawn to the screen whenever a graphics update occurs, depending on the graphics mode. When using dual-edge fast execution, the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 sprites have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x coordinate 1 (4), x coordinate 2 (4), y coordinate 1 (4), y coordinate 2 (4). The second coordinates are offset up by 1, to allow the full screen to be drawn to, such that the dimensions of the rectangle are (x2 - x1) + 1 and (y2 - y1) + 1. The next 16 bits are the sprites colour, with the first 15 bits being used for 15-bit direct colour, and the last bit being used to enable or disable drawing the sprite. The last bit is important to ensure that blank sprites are not drawn to the screen. Since the screen is not wiped every time it is refreshed, the background must be a sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed (see how Snake works). The sprites are drawn in memory order, with the sprite with the largest address always being drawn last and therefore on top, of all other sprites. This is achieved by using the exact same system as fast execution, which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically decreases the simulation's stack usage. 

Graphics (32x32): The Femto-4 can also drive a 32x32 screen, with sprites able to be drawn through 3 different modes. The 32x32 screen PPU treats the addresses as one combined 32-bit value, with the value with the smaller address going first. The first 3 bits of the 32 bits define the mode. Only the values 1, 2, 3, correspond to actual sprites, whilst the rest are not drawn to the screen. Mode 1 splits the remaining 29-bit space as the following: unused (1), x coordinate (5), y coordinate (5), red (6), green (6), blue (6). Mode 2 splits the 29-bit space in the following way: x coordinate 1 (5), x coordinate 2 (5), y coordinate 1 (5), y coordinate 2 (5), red (3), green (3), blue (3). Mode 3 splits the 29-bit space in the following way: unused (3), x coordinate (5), y coordinate (5), red (5), green (5), blue (5), alpha/transparency (1). As with the 16x16 screen, Mode 2's second coordinates are offset by 1 resulting in rectangles having the dimensions of (x1 - x2) + 1 and (y1 - y2) + 1. Mode 3 is designed to allow the colours used in the 16x16 screen to be the same, making converting code between the two versions easier. The update mechanism is the same as 16x16 screen. 

ALU: The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting, reducing the number of circuits required, as well as the logic required to decide which instruction to use. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the computer's graphics data. 

Conditional Jumps: The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. A similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not. Bit testing is most useful for testing an input from both controllers, since it can cut out an additional instruction. The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing: The computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. These pulses can tell registers to write and what source to write from, enable the read and write lines, update the ALU, and update the stack Each instruction is separate by 600k of delay in fast execution. For more information on how delay works see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction. 

Keyboard Mapping: The Femto-4's keyboard controller mapping was created using a specialised chip. This chip used the fast execution loop to take 15 inputs from a keyboard and map the inputs to button presses on the controllers. Since the buttons are updated several times in a clock pulse, the keyboard controller cannot handle held buttons. The keyboard mapping is designed to work with both controllers, allowing two player games to be feasible on the computer. 

Assembly: The Femto-4 has an assembler that converts assembly written in a .txt into hex values in a .txt that can be copied and loaded into the EEPROM banks for storage. The assembler can handle symbol assignment, as well as assigning addresses in the code symbols to make handling jumps easier. For full details on the Femto-4's assembly language view the assembly developer guide. 

Phemton: Phemton is the Femto-4's high level language, with a compiler to compile it's code into Femto-4 assembly. Phemton handles variable memory assignment, basic array assignment, if, elif, else statments, while loops, for loops, and functions. Phemton Lite is the only compiler complete, and lacks an optimiser. Phemton Lite has the concept of local scope only when compiling. All uniquely identified variables are given a global address. This reduces the runtime load since the computer does not need to decide where the variables need to go during run time. Future planned additions include generated code optimisations and optimisers, Phemton Full, which has dynamic memory assignment, and Phemton Plus, which adds additional types for floats and longs. For more details view Phemton's developer guide. 

Other Notes: The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. This makes it easy to additional chips to the computer. All assembly and Phemton code can be found in the project for the Femto-4's assembler and compiler respectively. The save data cart must be located outside of the Femto-4 circuit to ensure that its contents are automatically saved. Sorry about all the copies of this computer clogging up the top of the search results. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 

This is a secret to everybody, unless you found it. 

Latest versions of the 256-Series, including the Femto-4:
https://circuitverse.org/users/4699/projects/256-series

A 16-bit computer/maybe console inspired thing, the Femto-4. This is a branch to keep a functional version around. This project was started around November 2020.

Currently runs:
Cart A: Flappy Bird
Cart B: Some Pixel Art
Cart C: Screensaver
Cart D: Snake
Bundle Cart: All carts in one

Assembler:
https://repl.it/@Sanderokianstfe/Femto-4-Assembler#DeveloperGuide.txt

Features:
Immediate, direct and indirect memory access
Jumps and conditional Jumps
16-bit address space
Switchable Memory Banks, allowing for a standard cart to hold up to 512kx16b of data
An ALU capable of logical operators, addition, subtraction, shift left, shift right, multiplying, dividing, and other specialised functions
Easy to add to buses
"Fast Execution" - Can run more than one instruction per clock cycle
"Faster Execution" - Runs instructions on both edges of the clock pulse 
16x16 pixel display with 32 "Sprites" and 15-bit direct colour
Inputs, both "controllers" and keyboards
Random number generator
Text outputs
Stack
Von Neumann Architecture
Assembler (written in an external program)
Save memory
Four pre-written carts to play with

Previous Updates:
Fixed code controlled graphics updates
Made Bootloader clear TTY, Keyboard, and Controller Pushed
Fixed Register ALU instructions
Updated Cart A and Cart B to make use of the Register ALU instructions
Updated the Cart B to respond to the start button on both controllers
Moved to new project to fix issues around searching for projects branched from private projects
Removed unnecessary EEPROM banks from all carts
Removed unnecessary write lines leading to EEPROMs in carts, preventing code from being overwritten during execution
Made Reset clear WRAM and the General Registers
Fixed Keyboard
Added a Bundle Cart that allows you to view all the carts I have made without changing carts (you must reset the console to view another cart)
Fixed bug in standard bank design which wrote data to incorrect addresses
Fixed contention issue with multiplying
Added Annotations to the In Debug

Updates:
Added Snake Player
Added Reset and Power Labels to the relevant buttons

Will have:
More pre-written carts
Bug fixes

Do fork the project and write your own code for it! If you want more information on how to do so read the Developer Guide in the assembler. 

Note:
The Flappy Bird high score and the Snake high score are mine. If you want to save your own scores permanently you will have to fork the project. 

General Architecture:
The Femto-4 is a 16-bit computer with variable length instructions that are comprised of multiple 16-bit words. First the OP Code of the instruction is read, and then depending on the OP Code, additional pieces of data may be read for the operands. This allows execution to become incorrectly offset, which can lead to the execution of garbage if the PC is jumped to an incorrect address. This is usually fine, since the OP Code space is so empty that the data will likely be passed one at a time until the next valid instruction. Data is read through the standard data retrieval system (which is handy since its design is so universal and easy to add to) making this architecture a Von Neumann architecture as opposed to a Harvard architecture, like my previous, worse, computer. The MAR always specifies the address being read to or written from, whilst the MDR always holds the data being written. Data from the data out bus can be written to any special register during the instruction. OP Codes and operands are all 16-bits, which is a bit wasteful in terms of OP Code usage, however it was easier to implement this way, and so that is what I went with (and there are a lot of ALU processes). 

Memory Mapping:
The 16-bit address space of the Femto-4 is memory mapped, with all data being stored somewhere in the address space. The last 48kx16b of memory (all addresses starting with 01, 10, or 11) are dedicated to the cart memory. This is where the interchangeable program would be stored, allowing programs to be easily changed by changing carts. The carts have 32 16kx16b EEPROM/RAM chips, which can be switched between during execution by writing to address 00cc. This gives each cart 512kx16b of memory to play with. In theory, additional memory can be added in a cart by creating a similar system on the inside of the cart, which would allow it to swap between even more EEPROM/RAM chips. The initial 16kx16b are therefore mapped to everything else, including a fixed "work" RAM chip that cannot be switched out, the bootloader, the PPU data, general use registers, the, stack, inputs, outputs, and special use registers. 

"Fast Execution":
Execution at the fastest clock speed (one pulse every 100ms, or 10Hz, which is defined as the clock changing state every 50ms, or at a rate of 20Hz) is terribly slow, and would make reasonable graphics effectively impossible. Due to this, the Femto-4 includes several execution modes that allow the computer to run much faster. There are two registers involved in this, address 00ca, the mode register, and address 00cb, the protection register. When the two least significant bits of the mode register are low, the computer runs normally, executing 1 instruction per clock pulse. When it is set high however, the computer enters fast execution on the rising edge, where it executes multiple instructions per clock pulse. This is achieved by looping a rising edge monostable circuit into a falling edge monostable circuit, producing a loop that will pulse indefinitely until the looping line is written high to by some external factor. Stopping the loop is critical since leaving the loop running will stop CircuitVerse's execution, due to it going over the stack limit of the execution. "Fast execution" is always paused by a 0x0000 OP Code, which ensures that the computer will not attempt to "fast execute" memory that has not been written to. It is also paused by the OP Code 0x0001. Setting the 3 bit of the mode register high will enable protection. This will ensure that computer only executes as many instructions as the value in the protection register. This protects execution by ensuring that the loop will always pause before the cycle limit is reached. Since some operations are far more complex than other operations, the maximum number of instructions per clock pulse is variable, and testing should always be conducted to ensure that the limit is not reached. Due to this, for games that need regular graphics updates, it is recommended that protection is not used, and instead the pauses are fully code controlled. Setting the 2nd bit of the mode register high will enable the clock to run fast execution on the falling edge of the clock as well, doubling execution speed. On the other end of the mode register are the graphics mode. The highest two bits give the graphics update mode, 00 for falling edge only (normal speed), 01 for dual edge (double speed), 10 for every other clock pulse (half speed), and 11 for code controlled, where the 0x0001 OP Code is required to update the graphics. The third most significant bit is the graphics disable bit. Setting it high stops updating the graphics, reducing lag by reducing the number of changing outputs. The mode and protection values are only updated on the rising edge of the clock pulse, and therefore there should always be pauses before and after any execution mode or protection change. 

Graphics:
The Femto-4 is capable of driving a 16x16 15bit direct colour screen. It has space for 32 "sprites" which are rectangles with an assigned colour. All the sprites are drawn to the screen whenever a graphics update occurs, depending on the graphics mode. When using dual-edge "Faster Execution", the falling edge should only be used to execute game code, since writing graphics data as the screen is being drawn may mess up the graphics. These 32 "sprites" have their data stored in the PPU RAM in the following format: The first 16 bits are the corners of the rectangle, with each coordinate being 4 bits. The coordinates are ordered x1 x2 y1 y2. The next 16 bits are the sprites colour, with the first 15 bits being used for 15 bit direct colour, and the last bit being used to enable or disable drawing the sprite. Since the screen is not wiped every time it is refreshed, the background must be a sprite to ensure that the screen is fully wiped before the rest of the sprites are drawn on. Control of this allows carts to draw a single frame over multiple updates, allowing the 32-sprite limit to be bypassed (see how Snake works). The "sprites" are drawn in memory order, with the "sprite" with the largest address always being drawn last and therefore on top, of all other "sprites". This is achieved by using the exact same monostable clock system as "Fast Execution", which reads off all the sprite data and draws them to the screen in a single clock pulse. This can loop more times safely than the main CPU since it has less dependencies which dramatically decreases the simulation's stack usage. 

ALU:
The basic ALU was inspired by the ALU-74LS181. It was designed to flexibly change between various operations by changing an additional piece of data which is bundled in the OP Code. This allows a single ALU to handle all the required processes, such as the basic binary logic operations, shift left, adding, and subtracting. This is unlike my previous computer which had different chips for each operation it could do. The Femto-4 also can multiply, divide, shift right, shift left/right by a specified number of bits, and perform operations designed to work with the Femto-4's graphics data. 

Conditional Jumps:
The Femto-4 can perform immediate and direct jumps depending on the flags, a specified bit of the accumulator, and the clock. The flag jumps allow for comparisons to be made. There are three flags, the carry, the most significant bit in the accumulator, and if the accumulator value is 0, the equals flag. By performing A-B, we can compare A and B by looking at the flags. If the equals flag is true, then A=B, since A-B = 0. If the most significant bit is 0, then the number is positive or 0 (by two's complement) and therefore A>=B. The comparison is not entirely correct for numbers in two's complement (a large positive number and a large negative number when subtracted can yield a positive number), but for small values it works well. Whilst we cannot directly check A<=B using A-B in this design, we can simply flip the subtraction to B-A to do so. 
The accumulator bit testing is mainly used to check for controller inputs. Since each button in the controller is mapped to one bit, bit testing that bit effectively allows us to check if a button has been pressed. In theory a similar test could be performed using an AND instruction, and checking if the result is equal to 0 or not.
The jump on clock is there to ensure that we can jump execution on the right clock pulse, which ensures that graphics can be updated on the edge of execution. 

Timing:
This computer is timed using several standard delay chips. The pulse length running in to the computer is about 10k units long. Therefore, different parts an instruction are separated by 20k unit delays. Further control of timings inside these periods is achieved through 1k "On Delays", which have a 1k delay turning on, but a 0k delay turning off, ensuring that pulses do not bleed into the next pulse. These pulses can tell registers to write and what source to write from, enable the read and write lines, update the ALU, and update the stack. For more information on how delay works see here: https://circuitverse.org/users/4699/projects/circuitverse-delay-introduction. 

Other Notes:
The memory wrappers allow external chips to interact with the main data control system, in this case used for RNG, controllers, the keyboard, and driving the text output. This makes it easy to additional chips to the computer. 

For more information, please read the developer guide found in the Femto-4's Assembler, or just post a comment and ask me. 

This is a secret to everybody, unless you found it. 

16-bit program counter increments on rising-edge of CLK when COUNT=1. result: PC <-- PC + 1

Loads TARGET (from bus) when JUMP=1.  result: PC <-- TARGET

CLR for system reset. result: PC <-- 0

C_OUT to support extension from 16-bit to 32-bit

A 16-bit CPU

Hello,

I have built a fully working converter that converts 16-bit binary code to BCD.

I wanted a mode with a small amount of gates instead of millions of cells connected in series to ROM. As a result, I designed the converter in a slightly different way, using only 5 ROM cells, one register, one shift register and, of course, since this is an algorithm where the operation is performed by cyclically changing one piece of data, we also need a control unit. This is only for clock control and a few minor details.

This conversion method is generally referred to as double-dabble, also known as shift-and-add-3. In fact, it is a large number of ROM cells, each cell handling a 4-bit or BCD code. It works by adding 3 to all numbers greater than or equal to 5, then shifting the entire range of bits to the left once. This cycle is repeated as many times as the length of the input bits, for example we have 8 bits and the cycle will be repeated eight times.

The main difference between my converter and the others is that mine is done by a clock that is constantly blinking, and drives the cyclical circulation of a piece of data continuously across exactly the same pair of cells. This method reduces the number of gates, but may be slightly slower and more complicated. While other circuits are mostly built with series connected ROM cells and this results in a simple circuit but a higher gate count compared to mine.

Below I have attached an image of one ROM cell that converts binary code to BCD. There is also a table that describes the behaviour of this cell perfectly.

For a better user experience, don't forget to read the instructions below.

---

INSTRUCTIONS:
1. Reset your device before conversion!
    (RST = Reset button)
2. Enter the binary form of a number!
    (Input binary code)
3. Press the button to start the conversion!
    (BGN = Begin)
4. The clock must be on, it must blink 16 times!
    (CLK = Clock)
5. Read the BCD value!
    (Output BCD)

If you like my project, please give me a star (the button is on the bottom right), because it means a lot to me!

I hope you like the plan. I hope you enjoy the experience.

Hello,

I have designed a special converter. Converts a BCD or Binary Coded Decimal number to 16-bit binary logical number. The special feature is the surprising sequential entry of numbers!

This conversion method uses a small number of logic gates and the operation is cyclical, so a clock is essential. Each BCD value entry is equal to one cycle. The converter consists of a register called the Accumulator, a 16-bit full adder and a wire connection that correctly multiplies the number by 10. A small control unit is also needed to monitor the system.

An Accumulator is a type of register, usually the first one used to store results.

The device works by adding a value from 0 to 9 to each BCD input, storing it in a register and then multiplying by 10. The cycle is repeated for each entry. so, for example, the number 123 in the BCD value 0001 0010 0011 is sent sequentially to the converter. The first number sent will be 0001. The adder will add 0001, then store the value in a register and multiply it by 10 in the binary form 1010, and the result will be 1010. We will then send a second BCD number 0010. This number will be added to the previous stored number 1010 and the resulting number will be 1100. This number is again stored in the register and multiplied by 10 according to the current time, the result will be 1111000. Then send a third BCD value 0011, which is added to the stored value 1111000 to get 1111011. Now read our final result 1111011!

This converter design is quick and easy. Unlike the others, it converts sequential BCD input values and contains a small number of logic gates. Dabble Double algorithms exist for this conversion, but they behave differently.

I have attached a diagram of how the device works below. I hope it will help you with your planning!

INSTRUCTIONS:
1. Reset the device before use!
    (RST = Reset button)
2. Enter the BCD value!
    (Inpu BCD)
3. After each entry, send the value!
    (SND = Send)
4. Each entry is equal to one tick of the clock!
    (CLK = Clock)
5. The error will be logged!
    (E = Error)
6. Read the binary number!
    (Output binary)

If you like my project, please give me a star (the button is on the bottom right), because it means a lot to me!

I hope you like the plan. I hope you enjoy the experience.

Uses the divide by ten algorithm.

16 bit divider by Sanderokian Stfetoneri.

Femboy-16

Functional Electronic Machine Binary Operator Yes

A 16 bit CPU by Kain and Pacifiky

ABOUT

Made as a Successor to the FEMBOY-8.

A simple 16-bit calculator that can add and subtract two numbers together.

About the Combinox R1:

This is the third 16-bit CPU I have made. Its new name was inspired by the new combinational code. It is also my first computer to feature a graphics and base ten display. As a result of its brand new architecture, code, and clock it is much faster than my previous CPUs. 

Directions for use:

Choose the desired EEPROM program and insert it into the slot. First press the "RESET" button. Now press the "ON" button and enjoy your program.

Descriptions of programs:

blank: A blank EEPROM to be coded.

count up forever: Counts up by one until it reaches 65,535 then loops back to 0.

2+2: adds 2+2 and displays the output to the number display

transfer from keyboard to display: Displays the ascii value of whatever key is being entered on the keyboard.

random noise: Displays random noise on the screen.

Fibonacci: calculates the Fibonacci sequence 

Credits:

Sanderokian Stfetoneri - clock

Sanderokian Stfetoneri - 16 bit division

Example code (in Binary):

0000000001101000

0000000001101010

0000000000000001

Example code (in HEX):

0x68

0x6a

0x01

Example code (in asm):

SAVE 1101 R1

OUT R1

RST R1

Example code (explanation):

Saves "1101" in register 1

Outputs what's in register 1

Resets register 1

I'll add more instructions, functions and features in the future

** WIP** 

16-bit CPU with 8 Registers.

Architecture

• 4-bit opcode
• 0000 - Load mem to R0
• 0001 - CPY 
• 0010 - ALU
• 0011 - Compare
• 0100 - JMP NZ