Searched Projects

Tags: Gates

project.name
1 Stars     110 Views
User:
User Image Falko Schmidt

HPC0_S01_XOR

HPC0_S01_XOR
XOR Gates
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An XOR-Gate created using NOT, AND and OR gates.

project.name
0 Stars     110 Views
User:
User Image Falko Schmidt

Basic Gates

Basic Gates
Gates AND OR NOT
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This is just a simple project to get some practice with CircuitVerse and simple gates such as AND, OR, NOT.

project.name
0 Stars     71 Views
User:
User Image Tarun Gupta

Universal gate

Universal gate
Gates
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project.name
0 Stars     68 Views
User:
User Image Dip Bhowmick

CO LAB Exam

CO LAB Exam
lab1 Gates
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Learning Gates.

project.name
0 Stars     100 Views
User:
User Image Arslan Ashraf

DLD Lab 02

DLD Lab 02
Inverters Inputs Gates
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This is a 2x4 Decoder Logic Diagram.

project.name
0 Stars     46 Views
User:
User Image Shlok Dalvi

SIG

SIG
Gates
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project.name
0 Stars     72 Views
User:
User Image Zacharias Giannadakis

AND Gate

AND Gate
Gates
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project.name
0 Stars     65 Views
User:
User Image Zacharias Giannadakis

Not Gate

Not Gate
Gates
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project.name
0 Stars     101 Views
User:
User Image Sarvesh

isUppercase

isUppercase
Password Logic Gates
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Password Logic Gates

project.name
0 Stars     158 Views
User:
User Image Sarvesh

Special Characters

Special Characters
Password Logic Gates
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Special Characters

project.name
0 Stars     139 Views
User:
User Image Sarvesh

allAreOneofthem

allAreOneofthem
Password Logic Gates
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project.name
0 Stars     90 Views
User:
User Image Sarvesh

oneisUppercase

oneisUppercase
Password Logic Gates
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project.name
0 Stars     144 Views
User:
User Image Sarvesh

oneisLowercase

oneisLowercase
Password Logic Gates
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project.name
0 Stars     146 Views
User:
User Image Sarvesh

oneisSpecialCharacter

oneisSpecialCharacter
Password Logic Gates
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project.name
0 Stars     150 Views
User:
User Image Sarvesh

isValidPassword

isValidPassword
Password Logic Gates
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project.name
0 Stars     139 Views
User:
User Image Sarvesh

isOneofthem

isOneofthem
Password Logic Gates
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project.name
0 Stars     60 Views
User:
User Image Sandeep

Sandeep R

Sandeep R
Gates
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project.name
0 Stars     127 Views
User:
User Image SunnyMoon

NOT gate (only NAND)

NOT gate (only NAND)
Gates Nand Simple
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NOT gates are useless...


From NandGame.

project.name
0 Stars     121 Views
User:
User Image SunnyMoon

AND gate (only NAND)

AND gate (only NAND)
Gates Nand Simple
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AND gates are also useless...


From NandGame.

project.name
0 Stars     125 Views
User:
User Image SunnyMoon

OR gate (only NAND)

OR gate (only NAND)
Gates Nand Simple
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Pfft, who uses these gates?


From NandGame.

project.name
0 Stars     103 Views
User:
User Image SunnyMoon

XOR gate (only NAND)

XOR gate (only NAND)
Gates Nand Simple
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All of the gates (except good ol' NAND) are now useless, heh.


From NandGame.

project.name
0 Stars     93 Views
User:
User Image SunnyMoon

Full Adder (Only NAND)

Full Adder (Only NAND)
Arithmetic Addition Gates Nand
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Addition has never been so easy!


From NandGame.

project.name
1 Stars     93 Views
User:
User Image Rishabh Sharma

Project 1

Project 1
COA Project Project 1 Gates
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Aim :- Study and verify the outputs of the logic gates (AND, OR, NOT, NAND, NOR, Ex-OR, and Ex-NOR). 

project.name
0 Stars     44 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

EXP 1

EXP 1
Gates
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The NOT gate is called as an inverter. The output is high when the input is low. The output is low when the input is high. 

project.name
0 Stars     49 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

AB+BC+ABC

AB+BC+ABC
Gates
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AB(C+C')+BC(A+A')+ABC

ABC+ABC'+BCA+BCA'+ABC

ABC+ABC'+A'BC

project.name
0 Stars     41 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

EXP 2

EXP 2
Gates
View
project.name
0 Stars     47 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

EXP 3

EXP 3
Gates
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project.name
0 Stars     43 Views
User:
User Image Akezhan Rakishev

Lab 4 Ex 2

Lab 4 Ex 2
Gates
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project.name
0 Stars     38 Views
User:
User Image Sowmiya

Component1

Component1
Gates
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project.name
0 Stars     45 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

EXP 4

EXP 4
Gates
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project.name
0 Stars     42 Views
User:
User Image David Braga

TP0

TP0
Gates
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project.name
0 Stars     47 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

EXP 5

EXP 5
Gates
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project.name
0 Stars     45 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

EXP 6

EXP 6
Gates
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project.name
0 Stars     44 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

Assignment 1

Assignment 1
Gates
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project.name
1 Stars     99 Views
User:
User Image Roman

ALU

ALU
ALU Gates
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project.name
0 Stars     45 Views
User:
User Image S Harshit Venkatesh (RA1911018010068)

University Practical

University Practical
Gates
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project.name
0 Stars     28 Views
User:
User Image Nillohit Sharma

XOR GATE USING NAND GATE

XOR GATE USING NAND GATE
Gates
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project.name
0 Stars     70 Views
User:
User Image Anshuman Srivastava

Basic Logic Gates

Basic Logic Gates
Gates AND OR NOT XOR NAND NOR XNOR
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Basic circuits of all gates

project.name
1 Stars     48 Views
User:
User Image Aryan Upadhyay

Basic Gates

Basic Gates
Gates
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Basic gates in Digital Circuits.

project.name
0 Stars     91 Views
User:
User Image Aryan Upadhyay

ALL GATES USING NAND GATE

ALL GATES USING NAND GATE
Gates Nand
View

Making of all gates using NAND universal gate.

project.name
0 Stars     70 Views
User:
User Image Aryan Upadhyay

ALL GATES USING NOR GATE

ALL GATES USING NOR GATE
Gates NOR
View

All gates using NOR universal gate.

project.name
1 Stars     72 Views
User:
User Image Aryan Upadhyay

Adder Circuit

Adder Circuit
Gates Adder Circuit
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Half Adder : The addition of 2 bits is done using a combination circuit called Half adder. The input variables are augend and addend bits and output variables are sum & carry bits. A and B are the two input bits.

Full Adder Circuit : Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.

project.name
1 Stars     38 Views
User:
User Image Harsh Ponia

Gates (table varification)

Gates (table varification)
Gates verification of truth table
View

all gates varification truth table 

project.name
0 Stars     17 Views
User:
User Image Mehedi Hasan Hamim 1722059

Lab 1,Circuit 3 Simulation

Lab 1,Circuit 3 Simulation
Gates
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project.name
1 Stars     59 Views
User:
User Image Sarvadnya Sarode

Logic Gates

Logic Gates
Gates
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project.name
0 Stars     105 Views
User:
User Image Pritam K.

EXPERIMENT 1

EXPERIMENT 1
Gates Basic Gates Universal Gates
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Usage of Basic Gates and Universal Gates

project.name
0 Stars     53 Views
User:
User Image Meenal21050

NAND Implementation

NAND Implementation
Gates Nand
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Implemented NAND

project.name
0 Stars     49 Views
User:
User Image Abhishek Sushil

NOR Implement

NOR Implement
Gates Nor
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This is the implementation of NOR Gate

project.name
0 Stars     58 Views
User:
User Image Himanshu Choudhary

NAND AND NOR GATE

NAND AND NOR GATE
Gates Nand Nor
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project.name
0 Stars     24 Views
User:
User Image Christian Salumbides

CS111

CS111
Gates
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project.name
0 Stars     73 Views
User:
User Image Mubashir Jamali

Electronics_Basics

Electronics_Basics
Electronics Basics Gates Logic Design
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This project is made to teach/learn the basics of electronics, especially Digital Logic Design.

project.name
0 Stars     38 Views
User:
User Image Hamza Eldemery

The hidden language of comp hw and sw

The hidden language of comp hw and sw
Gates Adder
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project.name
0 Stars     30 Views
User:
User Image tasbeehkhaled

Gates

Gates
Gates
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project.name
0 Stars     22 Views
User:
User Image Murali Reddy G

Experiment 1 - Level 1

Experiment 1 - Level 1
Gates
View
project.name
0 Stars     25 Views
User:
User Image Akash

Logic Gates

Logic Gates
Gates
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project.name
0 Stars     23 Views
User:
User Image Ashutosh Gupta

LAB 1

LAB 1
Gates
View
project.name
0 Stars     23 Views
User:
User Image gaurav pandey

gaurav_pandey_gates_1

gaurav_pandey_gates_1
Gates
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And Gates perform all operations

project.name
0 Stars     21 Views
User:
User Image Kapil

AND GATE

AND GATE
Gates
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project.name
0 Stars     77 Views
User:
User Image SapereCircuit

JK FlipFlop NAND Gates (Rising edge)

JK FlipFlop NAND Gates (Rising edge)
FlipFlop JK positive logic NAND Gates JK FlipFlop sequential logic
View

This demonstrate the JK-Flipflop.

J 0, K 0 => do nothing
J 1, K 0 => Set (Q = 1, Q' = 0)
J 0, K 1 => Reset (Q = 0, Q' = 1)
J 1, K 1 => Toggle Q and Q'


project.name
0 Stars     71 Views
User:
User Image Mayank Gaur

Encoders

Encoders
Gates Encoder
View
project.name
0 Stars     41 Views
User:
User Image Mayank Gaur

Decoder

Decoder
Gates Decoder
View
project.name
0 Stars     37 Views
User:
User Image Mayank Gaur

Multiplexer

Multiplexer
Gates
View

4*1 and 8*1 Multiplexer

project.name
0 Stars     37 Views
User:
User Image Mayank Gaur

Demultiplexer

Demultiplexer
Gates
View

1*4 and 1*8 Demultiplexer

project.name
0 Stars     37 Views
User:
User Image Mayank Gaur

Flip Flops

Flip Flops
Gates
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SR and D Flip Flops

project.name
0 Stars     45 Views
User:
User Image Mayank Gaur

2-bit Arithmetic Logic Unit

2-bit Arithmetic Logic Unit
Gates MUX
View

2-bit Arithmetic Logic Unit

project.name
0 Stars     25 Views
User:
User Image Cepha G

Basic Gates

Basic Gates
Beginner Gates
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project.name
0 Stars     24 Views
User:
User Image N.Adithya Sharma

Basic_Gates

Basic_Gates
Gates
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All the basic Gates

project.name
0 Stars     23 Views
User:
User Image Adithya Viju

Assignment 1

Assignment 1
Gates
View
project.name
0 Stars     28 Views
User:
User Image rukhsar nadeem

AND Gate

AND Gate
AND Gates
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project.name
0 Stars     24 Views
User:
User Image Sri mugesh amrithan

Untitled

Untitled
Gates
View
project.name
0 Stars     24 Views
User:
User Image 625_Chinmayee R

Assignment_1

Assignment_1
Gates
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project.name
0 Stars     25 Views
User:
User Image Arbaaz saifi

All Gates

All Gates
Gates
View
project.name
0 Stars     40 Views
User:
User Image Pablo R. Gonzalez Q.

Clase 16 05112023

Clase 16 05112023
Gates Circuits Boolean Funciones Boolenas
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project.name
0 Stars     18 Views
User:
User Image Shreyas

Shreyas All Gates

Shreyas All Gates
Gates
View

nil

project.name
0 Stars     19 Views
User:
User Image Shreyas

Basic Gates Using NAND Gates

Basic Gates Using NAND Gates
Gates
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nil

project.name
0 Stars     16 Views
User:
User Image Shreyas

Basic Gates Using NOR Gates

Basic Gates Using NOR Gates
Gates
View

nil

project.name
0 Stars     16 Views
User:
User Image Shreyas

Basic Gates Using NOR Gates 2

Basic Gates Using NOR Gates 2
Gates
View

nil

project.name
0 Stars     25 Views
User:
User Image Shreyas hegde

Basic Gates Using NOR

Basic Gates Using NOR
Gates
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project.name
0 Stars     25 Views
User:
User Image Shreyas hegde

Basic Gates Using NAND

Basic Gates Using NAND
Gates
View
project.name
0 Stars     25 Views
User:
User Image Shreyas hegde

Every Gates

Every Gates
Gates
View
project.name
0 Stars     28 Views
User:
User Image Shreyas hegde

XOR using AND,NOT,OR

XOR using AND,NOT,OR
Gates
View
project.name
0 Stars     25 Views
User:
User Image Pavithra S

laws

laws
Gates
View
project.name
0 Stars     14 Views
User:
User Image Md. Rayhan

CAO HW

CAO HW
Gates
View

Gages: XOR, XNOR, Half-Adder, Full-Adder

project.name
0 Stars     28 Views
User:
User Image Rafael Sang-Yum

Basic Gates

Basic Gates
Basic Gates Learning 1
View
project.name
0 Stars     41 Views
User:
User Image APRI PANDU WICAKSONO

Praktikum Modul 1 UnGuided (PSD)

Praktikum Modul 1 UnGuided (PSD)
PSD Input Gates Output
View

Rangkaian gerbang logika untuk soal nomer 2, Buatlah suatu rangkaian logika (minimal menggunakan 4 gerbang logika) dan buatlah tabel 

kebenaran dari rangkaian yang dibuat!

project.name
0 Stars     25 Views
User:
User Image Eric Rodríguez

Odd Voting Circuit

Odd Voting Circuit
Logic Circuits Gates Circuit Votes
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Juan, Tadashi y Eric se reúnen una vez a la semana para ir al cine o pasear en bicicleta. Para decidir que hacer, utilizan un circuito digital en el que, por medio de botones, votan y de manera democrática el circuito les indica lo que van a hacer. El objetivo consiste en diseñar un circuito lógico que calcule de forma automática la decisión que se debe tomar.

project.name
0 Stars     30 Views
User:
User Image APRI PANDU WICAKSONO

Praktikum Modul 3 (PSD)

Praktikum Modul 3 (PSD)
PSD Input Gates Output
View

Rangkaian gerbang logika untuk membuat table kebenaran dan persamaan logika

project.name
0 Stars     37 Views
User:
User Image APRI PANDU WICAKSONO

Praktikum Modul 3 UnGuided (PSD)

Praktikum Modul 3 UnGuided (PSD)
PSD Input Gates Output
View

Jawaban soal modul 2, membuat rangkaian gerbang logika

project.name
0 Stars     30 Views
User:
User Image APRI PANDU WICAKSONO

Praktikum Modul 4 Part 1 (PSD)

Praktikum Modul 4 Part 1 (PSD)
PSD Input Gates Output
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Penyederhanaan persamaan rangkaian logika dan implementasi kedalam circuit menggunakan aljabar boolean

project.name
0 Stars     37 Views
User:
User Image APRI PANDU WICAKSONO

Praktikum Modul 4 Part 2 (PSD)

Praktikum Modul 4 Part 2 (PSD)
PSD Input Gates Output
View

Penyederhanaan persamaan rangkaian logika dan implementasi kedalam circuit menggunakan aljabar boolean

project.name
0 Stars     13 Views
User:
User Image nayan kumar m d

EXP 01

EXP 01
Gates
View
project.name
0 Stars     37 Views
User:
User Image APRI PANDU WICAKSONO

Praktikum Modul 5 (PSD)

Praktikum Modul 5 (PSD)
PSD Input Gates Output
View

Penyederhanaan persamaan rangkaian logika dan implementasi kedalam circuit menggunakan peta karnaugh

project.name
0 Stars     18 Views
User:
User Image Shubham Dutta

PracticeSet-01

PracticeSet-01
Gates
View

FIrst Project about Truth tables of gates.

project.name
0 Stars     8 Views
User:
User Image VEDANT DAFALE

Logic Gates

Logic Gates
Gates
View
project.name
0 Stars     6 Views
User:
User Image Mili Dholaria IT 045

LAB 1

LAB 1
Gates
View
project.name
0 Stars     17 Views
User:
User Image James Coombes

Logic Gate Challenges

Logic Gate Challenges
Digital Gates truth tables Karnagh K-maps boolean expressions
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Simplify logic gates using truth tables and Karnaugh mapping to find a reduced SOP expression and circuit.

project.name
0 Stars     13 Views
User:
User Image Abdulhadi Salama

Digital Design

Digital Design
Digital Clock Gates
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project.name
0 Stars     5 Views
User:
User Image Zakir M. Hamud

Gates

Gates
Gates
View
project.name
0 Stars     4 Views
User:
User Image Pablo R. Gonzalez Q.

Logic Gates 2024

Logic Gates 2024
Logic Binary Gates
View
project.name
0 Stars     4 Views
User:
User Image Pablo R. Gonzalez Q.

Circuito Digital

Circuito Digital
Gates And Or Xor Digital Logic
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