Combo Test 4

Combo Test 3

Decoder Multiplexor

2 to 7 Decoder AND Buffer for g

4 bit Counter

JK 3 Stage Counter

And Or Not Demo

2 to 7 Decoder (1,2,3,4)

SR Flip Flops

RockPaperScissorDecoder

Full Adder using 2 Half Adders

AND OR NOT

Full Adder using 2 Half Adders 2

Asynchrnous Up Counter

2 to 4 Decoder with ICs

DICE Project Phase 4

Rock Paper Scissor Input Encoder

UP/DOWN Counter

ALU with Registers

XOR Discrete to Adder

Detect Multiple HIGH Bits

4 Bit Adder

Adder Using Subcircuit

DICE Project Phase 6

Adder with Display Output

ALU (Decoder Multiplexor)

ABC + AB'(A'C')' Simplified

2 to 4 Decoder Clock Driven

8-Bit To BCD Converter

XOR Comparitor

Full Adder 2

DICE Display Decoded

Digital Clock Module (Seconds and Minutes)

2 Line to 4 Line Decoder Manual Counting

2 line to 7 Segment Counting

XOR Logic with more than two inputs

Rock Paper Sissor Multiple Switch Detection

Digital Dice Decoder Phase 2

2 Line to 4 Line Decoder

DICE Display with counter

DICE Reset Phase 5

2 line - 7 segment decoder

4 bit ALU

Test of Tri-State Buffer

RAM With Address Counter

Manual RAM Test

XOR to Half Adder

1 Bit Full Adder to 2 Bit Adder

4 Bit Adder/Subtractor 7 seg display

Four Bit Full Adder (Integrated)

4 to 16 line Decoder Demo

4 to 16 Line Subcircuit

4 to 16 line Decoder Detail

4 Bit Latch Prototype

4 Bit Latch Subcircuit

Moving Bar Display (2 bit)

4 Bit Transciever Sub Circuit

Tristate Latch 1

Bus Project 1

Multiplexors

2 bit ALU Phase 1

Tri-State Latch

Tri-State Latch 1

7 Seg Decoder

Demorgan Theorm 1

Double Dabble Module Part 2

2 Bit Adder

Double Dabble Circuit OLD 1

2 to 7 Line Decoder (Annotated)

Test Circuit 1

Logic Circuit Test 1

Tetra Counter

Demorgan Law

XOR using Descrete Components

Full Adder From Half Adders

XOR Logic Behavior

TD4 - 4bit cpu

XNOR Logic NAND

Digital Clock Module (Hours)

Adder/Subtractor

2-bit Arithmetic Logic Unit