4-Bit 7-Segment Display using only NAND
Full Subtractor using NAND Gates
Construction of Basic Gates, i.e. AND, OR, NOT, XOR using Universal Gate NAND
Implementation of SR FLIP-FLOP using SR-LATCH
Implementation of SR LATCH using NAND Gate
Implementation of D FLIP-FLOP Using SR-Latch and NAND Gates
Implementation of JK FLIP FLOP
Implementation of D FLIP-FLOP using JK FLIP-FLOP
Implementation of a T FLIP-FLOP using JK FLIP FLOP
Equivalencias a NAND de compuertas NOT, AND y OR para el trabajo Sumador de 4 bits con Compuertas Lógicas NAND.
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Estudiantes de la Universidad Nacional de Colombia. Semestre 2022-1. Asignatura Arquitectura de Computadores.
This demonstrate the JK-Flipflop.
J 0, K 0 => do nothing
J 1, K 0 => Set (Q = 1, Q' = 0)
J 0, K 1 => Reset (Q = 0, Q' = 1)
J 1, K 1 => Toggle Q and Q'