Searched Projects

Tags: NAND

project.name
0 Stars     90 Views
User:
User Image Arya Patel

LED_NAND

NAND
View
Here we have used NAND gate as the circuit intermediate. On one side of NAND gate there is LED and other side there are two input devices attached to it which give different input and as a result LED gives us the output.
project.name
0 Stars     64 Views
User:
User Image Arya Patel

AND_NAND

AND NAND
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Here, we have used NAND gate to derive the AND gate using 2 NAND gates.
project.name
0 Stars     49 Views
User:
User Image Arya Patel

OR_NAND

OR NAND
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Here, we have used 3 NAND gates to derive OR gate.
project.name
0 Stars     85 Views
User:
User Image Константин Дьяченко

All possible functions of one boolean argument using NAND gate

NAND
View
https://docs.google.com/spreadsheets/d/1_cedjiihoQCkkzHTgJ-hSHLCUhRXHaPbhZT1f0CxDoc
project.name
0 Stars     96 Views
User:
User Image Константин Дьяченко

All possible functions with two arguments built using NAND gates

NAND
View
Part 1: https://youtu.be/doHKPRt7oVo
Part 2: https://youtu.be/Wf4_BI0Ni3c
Functions: https://docs.google.com/spreadsheets/d/1tTTJzkWW9U1_2Y7GhNJUYV1NzlCdw87K10sv91FuykE
project.name
0 Stars     56 Views
User:
User Image Константин Дьяченко

16 functions with two arguments built using 14 NAND gates

NAND
View
https://youtu.be/gTFkdSTl7Ug
Functions: https://docs.google.com/spreadsheets/d/1yaYC6GCLoEN9eDn7LEegvsO5ePaBQ6bwXCmH-4zQHk0
project.name
0 Stars     58 Views
User:
User Image Константин Дьяченко

Simple 16 functions with two arguments built using 14 NAND gates

NAND
View
https://youtu.be/yyHd2UKErkA
Functions: https://docs.google.com/spreadsheets/d/1GiAXnaTXAUcgFKmCjEzwUsALLOG7dnfaSoeXQnN0Nm0
project.name
0 Stars     49 Views
User:
User Image Arya Patel

HalfAdder_NAND

HalfAdder NAND
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Here, we have used all the NAND gates to construct Half Adder using only two inputs.
project.name
0 Stars     20 Views
User:
User Image Georgia-Eirini Lazaridou

57838_πλήρης αθροιστής μιας θέσης με πύλες NAND,XOR

NAND XOR
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project.name
0 Stars     21 Views
User:
User Image Georgia-Eirini Lazaridou

57838_ημιαθροιστης με πύλες XOR,NAND,NOT

XOR NAND NOT
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project.name
0 Stars     14 Views
User:
User Image Diego

COMPUERTAS

AND OR NOT NOR NAND
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project.name
0 Stars     187 Views
User:
User Image NoNameSD

7 Segment Decoder (Only NAND)

4-Bit 7-Segment Seven Segment Seven Segment Decoder NAND
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4-Bit 7-Segment Display using only NAND

project.name
0 Stars     22 Views
User:
User Image Hassan

Decoder

decoder NAND IC.
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project.name
0 Stars     26 Views
User:
User Image Manav Majithia

XNOR USING NAND GATES

NAND XNOR XNOR USING NAND
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project.name
0 Stars     20 Views
User:
User Image Shatanshu Agarwal

Experiment-1

AND OR NOT NAND NOR XOR XNOR
View

1. AND

2. OR

3. NOT

4. NAND

5. NOR

6. XOR

7. XNOR

project.name
0 Stars     13 Views
User:
User Image Sanya Tyagi

GATES

AND OR NOT NAND NOR EX-OR EX-NOR
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project.name
0 Stars     14 Views
User:
User Image AKASHDEEP GUPTA

logic gates

(AND OR NOT NAND NOR Ex-OR and Ex-NOR).
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project.name
0 Stars     14 Views
User:
User Image Hanrui

NAND Gates

NAND gate
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project.name
0 Stars     23 Views
User:
User Image Sameer Alam

Basic gates from NAND gate

AND OR NOR NAND
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project.name
0 Stars     14 Views
User:
User Image Alfina Graceline J

AND

NAND NOR
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project.name
0 Stars     13 Views
User:
User Image Yadnika wagh

Basic Logic Gates

NOT AND OR NAND NOR XNOR
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This project is regarding OR , NOT , AND , NAND , NOR , XNOR , XOR ,

project.name
0 Stars     20 Views
User:
User Image Ujjwal Kar

Design and Realiization of Basic Logic gates

AND OR NOT NAND XOR
View

Design and Realiization of Basic Logic Gates

Name :- Ujjwal Kar

Roll No. :- 12100119047
Dept. :- CSE (A)


project.name
0 Stars     14 Views
User:
User Image D_2061008_M.Maria Anish

aMISH Q1

QUESTION 1 NAND NOR XNOR
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project.name
0 Stars     15 Views
User:
User Image D_2061008_M.Maria Anish

2061008 m.anish q4

q4 AND NAND NOR
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q4

project.name
0 Stars     14 Views
User:
User Image SUBHENDU DALAI 2047024

2047024_xor_using_nand

XOR NAND
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project.name
0 Stars     13 Views
User:
User Image ROHITHA KA

FAMILIRIZATION OF LOGIC GATES

OR AND NAND NOT NOR
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project.name
0 Stars     14 Views
User:
User Image ANUSHIKA P J

FAMILIARISATION OF CIRCUITS

AND OR NAND NOR XNOR XOR NOT
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Result: Familiarisation with logic gates through virtual lab successfully completed.

project.name
0 Stars     21 Views
User:
User Image ANUSHIKA P J

FAMILIARISATION OF LOGIC GATES USING UNIVERSAL GATES

AND OR NAND NOR XNOR XOR NOT USING NAND AND NOR
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RESULT: Familiarised different logic gates using universal gates (AND gate only as well as NOR gate) using virtual lab.

project.name
0 Stars     16 Views
User:
User Image ANUSHIKA P J

HALF AND FULL ADDER

AND OR NAND NOR XNOR XOR NOT
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Successfully completed half and full adder using gates and universal gates.

project.name
0 Stars     14 Views
User:
User Image Jasper Ian Guanlao

Flip-Flops

Flip Flops S-C S-R J-K NAND NOR Clock T D
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Flipflops

project.name
0 Stars     14 Views
User:
User Image Uğurcan Erdoğan

NAND GATE and derivatives

nand NAND gate boolean
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project.name
0 Stars     27 Views
User:
User Image Chrilosoph

ALU_ROrg2021

ALU AND OR NAND NOR ADD SUB
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Rechnerorganisation TU Berlin WS2021

project.name
0 Stars     13 Views
User:
User Image Rohit Kumar Chaurasia

lOGIC GATES

AND OR NOT XOR NAND NOR XNOR
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project.name
0 Stars     13 Views
User:
User Image Priyanka Raghuvanshi

GATES

OR AND NOT NAND XOR XNOR GATES
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project.name
0 Stars     13 Views
User:
User Image Narendran S

Logic GATES

logic gates AND OR NOT EXOR NAND NOR
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project.name
0 Stars     18 Views
User:
User Image Michelle Lo

From NAND to Tetris Ch.1

NOT AND NAND OR NOR XOR XNOR
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project.name
0 Stars     19 Views
User:
User Image Joshua Bettigole

NAND Example

NAND
View

Example NAND gate

project.name
0 Stars     10 Views
User:
User Image 340_Sajia Bintea Jahangir

Verify the univarsality of NAND & NOR gates

NAND NOR
View

Experiment 1

project.name
0 Stars     13 Views
User:
User Image Atia Rahman Orthi

Universal Gate

NAND
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project.name
0 Stars     15 Views
User:
User Image 356_Mangsura Kabir Oni

Experiment-1(Basic Gates)

AND OR NOT NAND NOR Gates
View

Introduction to logic gates and it's verification with truth table.

project.name
0 Stars     15 Views
User:
User Image Chirantan Basu

CO LAB

AND OR NOT NAND NOR XOR XNOR HALF ADDER HALF SUBTRACTOR FULL ADDER FULL SUBTRACTOR RIPPLE CARRY ADDER BCD CARRY LOOK AHEAD BINARY INCREMENTER BINARY DECREMENTER ADDER SUBTRACTOR 4:2 DECODER 2:1MUX
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project.name
0 Stars     10 Views
User:
User Image YAZID K P (RA1911018010071)

EXPERIMENT 1 A

AND OR NAND NOT NOR XOR X-NOR A
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project.name
0 Stars     8 Views
User:
User Image Anmol Kumar Shrivastava

Gates

NAND
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project.name
0 Stars     8 Views
User:
User Image Anmol Kumar Shrivastava

GATE

NAND
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project.name
0 Stars     8 Views
User:
User Image Anmol Kumar Shrivastava

Gates

AND NAND NOR OR
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project.name
0 Stars     13 Views
User:
User Image Alexandru Ghisa

BCD NAND

7 Segment Display NAND
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project.name
0 Stars     12 Views
User:
User Image Alexandru Ghisa

BCH NAND

7 Segment Display NAND
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project.name
0 Stars     11 Views
User:
User Image Prince Kumar Deka

RS latch

RS Latch NAND
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RS latch using NAND and NOR gates

project.name
0 Stars     6 Views
User:
User Image CA SIS

Gates

NOT OR NAND
View

Puertas Logicas

project.name
0 Stars     11 Views
User:
User Image JOEL GREGORY RAJAN MBT19CS067

Verifying basic Gates

AND NAND OR NOR NOT XOR XNOR
View

Verifying the truth tables of Basic and Universal Gates

project.name
0 Stars     7 Views
User:
User Image P HYAREEN LINDA MBT19CS092

Verifying Basic Gates

AND OR NOT NOR NAND XOR XNOR
View
project.name
0 Stars     9 Views
User:
User Image Varun Ajith Sivaram

Verifying Basic Gates

AND OR NOT NAND NOR XOR XNOR
View

Verification of basic gates

project.name
0 Stars     7 Views
User:
User Image MBT19CS119 VAISAKH R S

Verifying basic gates

AND NAND OR NOR NOT XOR XNOR
View

Representation of 7 logic gates.

project.name
0 Stars     5 Views
User:
User Image YASHWANTH KRISHNAN B

LOGIC GATES

AND OR NOT NAND NOR
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project.name
0 Stars     5 Views
User:
User Image Vivek Kumar

Verification of gates

AND NOT OR NAND NOR XOR
View

verification of truth table

project.name
0 Stars     5 Views
User:
User Image RAJ KUMAR

Al gates verify

AND OR NOR NAND NOT
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project.name
0 Stars     5 Views
User:
User Image chiranjeevi

logic gates

NOT AND OR XOR NAND NOR XNOR Gates
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project.name
0 Stars     7 Views
User:
User Image Umesh

Experiment 1

AND OR NOT NAND NOR XOR XNOR
View

project.name
0 Stars     6 Views
User:
User Image Anshuman Srivastava

Basic Logic Gates

Gates AND OR NOT XOR NAND NOR XNOR
View

Basic circuits of all gates

project.name
0 Stars     7 Views
User:
User Image SHIVANAND JHA

Basic Logic Gates

NOT AND OR NAND NOR XNOR XOR.
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project.name
0 Stars     5 Views
User:
User Image 2060655_Gaurav singh

Experiment 1

Q1:- Realize the truth table for AND OR NOT NAND NOR EXOR Q2:- Obtain the output for y=(AB+C)'+(A'+B'+C')
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project.name
0 Stars     3 Views
User:
User Image 2141039

2141039_q4

NAND
View

2141039 Sourav Kumar Question No.4

project.name
0 Stars     4 Views
User:
User Image KRISHNAPRIYA M S

EXPERIMENT:1

LOGIC GATES [NOT AND OR NOR NAND EX-OR]
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project.name
0 Stars     7 Views
User:
User Image Sharmistha Mondal 12

LOGIC

AND OR NOT NAND NOR XOR XNOR
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project.name
0 Stars     12 Views
User:
User Image Sharmistha Mondal 12

LOGIC

AND OR NOT NAND NOR XOR XNOR
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project.name
0 Stars     8 Views
User:
User Image MUHAMMED ANAS P

experiment 1

to familiarize the gates (NOT NOR XOR AND NAND OR)
View
project.name
0 Stars     4 Views
User:
User Image shanoon m

EXPERIMENT 1

LOGIC GATES[NOT OR NOR NAND EX-OR]
View

SREELAKSHMI M

project.name
1 Stars     5 Views
User:
User Image shanoon m

EXPERIMENT 1

LOGIC GATES[NOT OR NOR NAND EX-OR]
View

Sreelakshmi M

project.name
1 Stars     4 Views
User:
User Image shanoon m

EXPERIMENT 1

LOGIC GATES[NOT OR NOR NAND EX-OR]
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project.name
0 Stars     4 Views
User:
User Image shanoon m

EXPERIMENT 1

LOGIC GATES[NOT OR NOR NAND EX-OR]
View
project.name
0 Stars     3 Views
User:
User Image shanoon m

EXPERIMENT 1

LOGIC GATES[NOT OR NOR NAND EX-OR]
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project.name
0 Stars     3 Views
User:
User Image shanoon m

EXPT NO 2

LOGIC GATES[NOT OR NOR NAND EX-OR]
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project.name
0 Stars     3 Views
User:
User Image Himanshu Mishra

first

AND OR NOT NAND NOR XOR XNOR
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project.name
0 Stars     3 Views
User:
User Image Lorenzo Murillo IV

NAND to AND

NAND AND
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project.name
0 Stars     3 Views
User:
User Image Lorenzo Murillo IV

NAND to NOT

NAND NOT
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project.name
0 Stars     4 Views
User:
User Image Lorenzo Murillo IV

NAND to OR

NAND OR
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project.name
0 Stars     5 Views
User:
User Image Lorenzo Murillo IV

NAND to NOR

NAND NOR
View
project.name
0 Stars     4 Views
User:
User Image Lorenzo Murillo IV

NAND to XOR

NAND XOR
View
project.name
0 Stars     3 Views
User:
User Image Lorenzo Murillo IV

NAND to XNOR

NAND XNOR
View
project.name
0 Stars     3 Views
User:
User Image Lorenzo Murillo IV

NOR to NAND

NOR NAND
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project.name
0 Stars     3 Views
User:
User Image AnupamSingh_30042

Exp1

AND OR NOT XOR XNOR NAND NOR
View
project.name
0 Stars     5 Views
User:
User Image Ayush Raj

Logic Gates

AND OR NOT NOR NAND XOR XNOR
View
project.name
0 Stars     4 Views
User:
User Image Fiza0069

CIRCUIT DIAGRAM

AND OR NOT NAND NOR XOR XNOR
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project.name
0 Stars     3 Views
User:
User Image Mahima

GATES

AND OR NOR NAND XOR XNOR NOT
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project.name
0 Stars     22 Views
User:
User Image Jahid

DL_CO_Full_Subtractor_NAND_2147033

Subtractor NAND Full Subtractor
View

Full Subtractor using NAND Gates

project.name
0 Stars     4 Views
User:
User Image Kshitij Goyal

Gates

OR AND NOT NOR NAND XOR XNOR
View

OR,AND,NOT,NOR,NAND,XOR,XNOR

project.name
0 Stars     1 Views
User:
User Image Harsha Challagulla

SR Latch

SR LATCH NOR NAND
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project.name
0 Stars     2 Views
User:
User Image GURAMPATI SRINIVASULUREDDY

GATES

AND OR NOT NAND NOR XOR
View
project.name
0 Stars     2 Views
User:
User Image Seethal S

Familiarization of gates

AND OR NOT NOR NAND XOR XNOR
View
project.name
0 Stars     2 Views
User:
User Image Amit Kumar

NOR GATE

NOT OR NAND NOR XOR XNOR
View

NOR GATE AS UNIVERSAL GATE

project.name
0 Stars     1 Views
User:
User Image Pritam K.

EXPERIMENT 1A

Basic Gates Universal Gates NAND NOT OR AND
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Construction of Basic Gates, i.e. AND, OR, NOT, XOR using Universal Gate NAND

project.name
0 Stars     1 Views
User:
User Image Pritam K.

EXPERIMENT 21

SR LATCH SR FLIP FLOP SEQUENTIAL CIRCUIT FLIP FLOP NAND
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Implementation of SR FLIP-FLOP using SR-LATCH

Implementation of SR LATCH using NAND Gate

project.name
0 Stars     1 Views
User:
User Image Pritam K.

EXPERIMENT 22

SR LATCH D FLIP FLOP SEQUENTIAL CIRCUIT FLIP FLOP NAND
View

Implementation of D FLIP-FLOP Using SR-Latch and NAND Gates

project.name
0 Stars     1 Views
User:
User Image Pritam K.

EXPERIMENT 23

SR LATCH JK FLIP FLOP SEQUENTIAL CIRCUIT FLIP FLOP NAND
View

Implementation of JK FLIP FLOP

project.name
0 Stars     1 Views
User:
User Image Pritam K.

EXPERIMENT 23 MISC

D FLIP FLOP JK FLIP FLOP SR LATCH SEQUENTIAL CIRCUIT FLIP FLOP NAND
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Implementation of D FLIP-FLOP using JK FLIP-FLOP

project.name
0 Stars     1 Views
User:
User Image Pritam K.

EXPERIMENT 24

T FLIP FLOP JK FLIP FLOP SR LATCH SEQUENTIAL CIRCUIT FLIP FLOP NAND
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Implementation of a T FLIP-FLOP using JK FLIP FLOP

project.name
0 Stars     1 Views
User:
User Image Abhishek Mishra

Universal Gates

NAND NOR
View

Working properly


project.name
0 Stars     3 Views
User:
User Image Florence Ighravwe

Logic gates

AND NAND OR NOR NOT XOR XNOR
View

These are logic gates

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