Searched Projects

Tags: NAND

project.name
0 Stars     59 Views
User:
User Image Arya Patel

LED_NAND

NAND
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Here we have used NAND gate as the circuit intermediate. On one side of NAND gate there is LED and other side there are two input devices attached to it which give different input and as a result LED gives us the output.
project.name
0 Stars     53 Views
User:
User Image Arya Patel

AND_NAND

AND NAND
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Here, we have used NAND gate to derive the AND gate using 2 NAND gates.
project.name
0 Stars     38 Views
User:
User Image Arya Patel

OR_NAND

OR NAND
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Here, we have used 3 NAND gates to derive OR gate.
project.name
0 Stars     78 Views
User:
User Image Константин Дьяченко

All possible functions of one boolean argument using NAND gate

NAND
View
https://docs.google.com/spreadsheets/d/1_cedjiihoQCkkzHTgJ-hSHLCUhRXHaPbhZT1f0CxDoc
project.name
0 Stars     88 Views
User:
User Image Константин Дьяченко

All possible functions with two arguments built using NAND gates

NAND
View
Part 1: https://youtu.be/doHKPRt7oVo
Part 2: https://youtu.be/Wf4_BI0Ni3c
Functions: https://docs.google.com/spreadsheets/d/1tTTJzkWW9U1_2Y7GhNJUYV1NzlCdw87K10sv91FuykE
project.name
0 Stars     50 Views
User:
User Image Константин Дьяченко

16 functions with two arguments built using 14 NAND gates

NAND
View
https://youtu.be/gTFkdSTl7Ug
Functions: https://docs.google.com/spreadsheets/d/1yaYC6GCLoEN9eDn7LEegvsO5ePaBQ6bwXCmH-4zQHk0
project.name
0 Stars     54 Views
User:
User Image Константин Дьяченко

Simple 16 functions with two arguments built using 14 NAND gates

NAND
View
https://youtu.be/yyHd2UKErkA
Functions: https://docs.google.com/spreadsheets/d/1GiAXnaTXAUcgFKmCjEzwUsALLOG7dnfaSoeXQnN0Nm0
project.name
0 Stars     42 Views
User:
User Image Arya Patel

HalfAdder_NAND

HalfAdder NAND
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Here, we have used all the NAND gates to construct Half Adder using only two inputs.
project.name
0 Stars     14 Views
User:
User Image Georgia-Eirini Lazaridou

57838_πλήρης αθροιστής μιας θέσης με πύλες NAND,XOR

NAND XOR
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project.name
0 Stars     15 Views
User:
User Image Georgia-Eirini Lazaridou

57838_ημιαθροιστης με πύλες XOR,NAND,NOT

XOR NAND NOT
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project.name
0 Stars     8 Views
User:
User Image Diego

COMPUERTAS

AND OR NOT NOR NAND
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project.name
0 Stars     126 Views
User:
User Image NoNameSD

7 Segment Decoder (Only NAND)

4-Bit 7-Segment Seven Segment Seven Segment Decoder NAND
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4-Bit 7-Segment Display using only NAND

project.name
0 Stars     13 Views
User:
User Image Hassan

Decoder

decoder NAND IC.
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project.name
0 Stars     16 Views
User:
User Image Manav Majithia

XNOR USING NAND GATES

NAND XNOR XNOR USING NAND
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project.name
0 Stars     12 Views
User:
User Image Shatanshu Agarwal

Experiment-1

AND OR NOT NAND NOR XOR XNOR
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1. AND

2. OR

3. NOT

4. NAND

5. NOR

6. XOR

7. XNOR

project.name
0 Stars     7 Views
User:
User Image Sanya Tyagi

GATES

AND OR NOT NAND NOR EX-OR EX-NOR
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project.name
0 Stars     7 Views
User:
User Image AKASHDEEP GUPTA

logic gates

(AND OR NOT NAND NOR Ex-OR and Ex-NOR).
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project.name
0 Stars     8 Views
User:
User Image Hanrui

NAND Gates

NAND gate
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project.name
0 Stars     14 Views
User:
User Image Sameer Alam

Basic gates from NAND gate

AND OR NOR NAND
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project.name
0 Stars     6 Views
User:
User Image Alfina Graceline J

AND

NAND NOR
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project.name
0 Stars     7 Views
User:
User Image Yadnika wagh

Basic Logic Gates

NOT AND OR NAND NOR XNOR
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This project is regarding OR , NOT , AND , NAND , NOR , XNOR , XOR ,

project.name
0 Stars     14 Views
User:
User Image Ujjwal Kar

Design and Realiization of Basic Logic gates

AND OR NOT NAND XOR
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Design and Realiization of Basic Logic Gates

Name :- Ujjwal Kar

Roll No. :- 12100119047
Dept. :- CSE (A)


project.name
0 Stars     8 Views
User:
User Image D_2061008_M.Maria Anish

aMISH Q1

QUESTION 1 NAND NOR XNOR
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project.name
0 Stars     8 Views
User:
User Image D_2061008_M.Maria Anish

2061008 m.anish q4

q4 AND NAND NOR
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q4

project.name
0 Stars     8 Views
User:
User Image SUBHENDU DALAI 2047024

2047024_xor_using_nand

XOR NAND
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project.name
0 Stars     7 Views
User:
User Image ROHITHA KA

FAMILIRIZATION OF LOGIC GATES

OR AND NAND NOT NOR
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project.name
0 Stars     8 Views
User:
User Image ANUSHIKA P J

FAMILIARISATION OF CIRCUITS

AND OR NAND NOR XNOR XOR NOT
View

Result: Familiarisation with logic gates through virtual lab successfully completed.

project.name
0 Stars     11 Views
User:
User Image ANUSHIKA P J

FAMILIARISATION OF LOGIC GATES USING UNIVERSAL GATES

AND OR NAND NOR XNOR XOR NOT USING NAND AND NOR
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RESULT: Familiarised different logic gates using universal gates (AND gate only as well as NOR gate) using virtual lab.

project.name
0 Stars     9 Views
User:
User Image ANUSHIKA P J

HALF AND FULL ADDER

AND OR NAND NOR XNOR XOR NOT
View

Successfully completed half and full adder using gates and universal gates.

project.name
0 Stars     8 Views
User:
User Image Jasper Ian Guanlao

Flip-Flops

Flip Flops S-C S-R J-K NAND NOR Clock T D
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Flipflops

project.name
0 Stars     7 Views
User:
User Image Uğurcan Erdoğan

NAND GATE and derivatives

nand NAND gate boolean
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project.name
0 Stars     13 Views
User:
User Image Chrilosoph

ALU_ROrg2021

ALU AND OR NAND NOR ADD SUB
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Rechnerorganisation TU Berlin WS2021

project.name
0 Stars     7 Views
User:
User Image Rohit Kumar Chaurasia

lOGIC GATES

AND OR NOT XOR NAND NOR XNOR
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project.name
0 Stars     5 Views
User:
User Image Priyanka Raghuvanshi

GATES

OR AND NOT NAND XOR XNOR GATES
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project.name
0 Stars     6 Views
User:
User Image Narendran S

Logic GATES

logic gates AND OR NOT EXOR NAND NOR
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project.name
0 Stars     7 Views
User:
User Image Michelle Lo

From NAND to Tetris Ch.1

NOT AND NAND OR NOR XOR XNOR
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project.name
0 Stars     13 Views
User:
User Image Joshua Bettigole

NAND Example

NAND
View

Example NAND gate

project.name
0 Stars     4 Views
User:
User Image 340_Sajia Bintea Jahangir

Verify the univarsality of NAND & NOR gates

NAND NOR
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Experiment 1

project.name
0 Stars     5 Views
User:
User Image Atia Rahman Orthi

Universal Gate

NAND
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project.name
0 Stars     5 Views
User:
User Image 356_Mangsura Kabir Oni

Experiment-1(Basic Gates)

AND OR NOT NAND NOR Gates
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Introduction to logic gates and it's verification with truth table.

project.name
0 Stars     6 Views
User:
User Image Chirantan Basu

CO LAB

AND OR NOT NAND NOR XOR XNOR HALF ADDER HALF SUBTRACTOR FULL ADDER FULL SUBTRACTOR RIPPLE CARRY ADDER BCD CARRY LOOK AHEAD BINARY INCREMENTER BINARY DECREMENTER ADDER SUBTRACTOR 4:2 DECODER 2:1MUX
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project.name
0 Stars     4 Views
User:
User Image YAZID K P (RA1911018010071)

EXPERIMENT 1 A

AND OR NAND NOT NOR XOR X-NOR A
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project.name
0 Stars     3 Views
User:
User Image Anmol Kumar Shrivastava

Gates

NAND
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project.name
0 Stars     3 Views
User:
User Image Anmol Kumar Shrivastava

GATE

NAND
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project.name
0 Stars     3 Views
User:
User Image Anmol Kumar Shrivastava

Gates

AND NAND NOR OR
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project.name
0 Stars     5 Views
User:
User Image Alexandru Ghisa

BCD NAND

7 Segment Display NAND
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project.name
0 Stars     6 Views
User:
User Image Alexandru Ghisa

BCH NAND

7 Segment Display NAND
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project.name
0 Stars     3 Views
User:
User Image Prince Kumar Deka

RS latch

RS Latch NAND
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RS latch using NAND and NOR gates

project.name
0 Stars     3 Views
User:
User Image CA SIS

Gates

NOT OR NAND
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Puertas Logicas

project.name
0 Stars     2 Views
User:
User Image JOEL GREGORY RAJAN MBT19CS067

Verifying basic Gates

AND NAND OR NOR NOT XOR XNOR
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Verifying the truth tables of Basic and Universal Gates

project.name
0 Stars     1 Views
User:
User Image P HYAREEN LINDA MBT19CS092

Verifying Basic Gates

AND OR NOT NOR NAND XOR XNOR
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project.name
0 Stars     3 Views
User:
User Image Varun Ajith Sivaram

Verifying Basic Gates

AND OR NOT NAND NOR XOR XNOR
View

Verification of basic gates

project.name
0 Stars     1 Views
User:
User Image MBT19CS119 VAISAKH R S

Verifying basic gates

AND NAND OR NOR NOT XOR XNOR
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Representation of 7 logic gates.

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