Futurelearn Course - How Computers Work
Basic Gates
4 bits Left/Right Shiftcounter
Other than most designs this design uses the principal of a shift-register instead of a counter. I need less components.
Logic gates
logic gates
adders
exaple1
example
5001_Aagash/Exercise-1 Verification of logic gates
full adder using logic gates
Half adder
This circuit is regarding half adder.
Full adder using basic gates
full adder,logic gates
A computer made completely out of logic gates. Version 2. V1 can be found here: https://circuitverse.org/users/13948/projects/49969
Because of the limitations of the circuitverse.org simulator, and for easier use, some inbuilt components are used (like the 256-byte RAM module), but most of it is made up of OR, AND, NOT, XOR, NOR and NAND.
This project was originally made for my profile project. This is (or will be) version 2 of the 8-bit computer.
FULL ADDER
The complete adder can be realized using two semi-adders, the logic scheme is presented. Note that there is a common XOR circuit in the expressions: i and a ⊕b, so there may be this convenience
using to perform small cobra functions using an even smaller number of circuits.
Computational logic
1 bit full adder circuit with numerical output display
logic gates(058)
logic gates
logic gates
XOR
Puerta lógica XOR
n bit ripple carry adder
n bit triple order
Basic
Sumador 2bit
Puerta mixta AND/XOR + puerta OR
expriment1:All logic gates
Assignment 2
my 2 nd assignment
To laugh or not to laugh?
you should laugh at a joke if it is funny, it is in good taste and it is not offensive to others or, if it is told by your professor (Regardless of it being funny or being in good taste) and it is not offensive to others. implement the situation using logic gates
Excuse me? Who let you in?
The company safe should be unlocked only when Mr. jones is in the office or Mr. Evans is in the office, and only when the company is open for business and only when the security guard is present. implement only using NAND gates
PRASANTH S
8x1 Multiplexer
8x1 multiplexer has 8 data input lines I0, I1, I2, I3, I4, I5, I6, I7, 3 select lines S0, S1, S2 and one output, Y.
Truth Table for 8x1 Multiplexer
Data Select Input
Output
Y
S2
S1
S0
0
0
0
I0
0
0
1
I1
0
1
0
I2
0
1
1
I3
1
0
0
I4
1
0
1
I5
1
1
0
I6
1
1
1
I7
De Multiplexer
1x8 de multiplexer has 1 input line I, 3 select lines S0,
S1, S2 and 8 outputs Y0, Y1, Y2,
Y3, Y4,Y5,
Y6, Y7
Truth Table of 1x8 DE MUX
Input
Data
S2
S1
S0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
D
0
0
0
D
0
0
0
0
0
0
0
D
0
0
1
0
D
0
0
0
0
0
0
D
0
1
0
0
0
D
0
0
0
0
0
D
0
1
1
0
0
0
D
0
0
0
0
D
1
0
0
0
0
0
0
D
0
0
0
D
1
0
1
0
0
0
0
0
D
0
0
D
1
1
0
0
0
0
0
0
0
D
0
D
1
1
1
0
0
0
0
0
0
0
D
SR Flip Flop
The basic NAND gate RS flip flop circuit is used to store the data and thus provides feedback from both of its outputs again back to its inputs. The RS flip flop actually has three inputs, SET, RESET and its current output Q relating to its current state.
Truth Table for RS flip –flop
Clk
R
S
Q
Q’
0
X
X
Previous or Memory State
1
1
0
0
1
1
0
1
1
0
1
0
0
Previous or Memory State
1
1
1
Invalid State
D flip-flop
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by connecting the R input through an inverter, and the S input is connected directly to data input. The modified clocked SR flip-flop is known as D-flip-flop and is shown below. From the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs are same and high. In many practical applications, these input conditions are not required. These input conditions can be avoided by making them complement of each other.
Truth Table for D flip-flop
Clk
D
Q
Q’
0
1
Previous or memory state
0
1
1
0
0
1
1
1
1
0
JK flip-flop
In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be re-joined if both inputs are 1 than also the outputs are complement of each other as shown in characteristics table below.
Truth Table for JK flip-flop
Input
Output
Clk
J
K
Q
Q’
0
X
X
Previous or Memory State
1
1
0
1
0
1
0
1
0
1
1
0
0
Previous or Memory State
1
1
1
Toggle State
T flip-flop
T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to change as shown in table below.
Truth Table of T flip-flop
Clk
T
Q
Q’
0
1
Previous or memory state
0
0
1
0
1
1
Toggle state
expt1
fibonatti number detector
Circuit that detects if a number, encoded in binary (4 bits) belongs to the Fibonatti's sequence.
Circuito que detecta se um número codificado em 4 bits pertence a sequência de Fibonatti (in portuguese).
20BEI016 EX NO.1
LOGIC GATES
20BEI016_DE_EX NO.1
LOGIC GATES
Contador 1-9
Es un contador del 1-9
logic gates
FCO - Practice 2
Here is all of the 2º practice
END SEM LAB
NAND blocks
Gates
logic gates
7 segment decoder
Verification of Logic gates
8 digit adder
first logic
memory Latch
This is a memory latch that can reliably store one digit. When you store 1, the light is on. If you store 0, the light stays off. This may be confusing for some, but play around to see how you can store a digit.
( HINT: the set memory button will allow you to store a new number when it is on 1. When the set memory button is set as 0, you cannot make any modification to the stored memory. Use the ´stored memory´ button to toggle the digit you are storing)
circuit gates
Dilip jadahv
Dilip
Experiment 1
sayed rafat ali
Untitled
This is to undestand the various logic gates
Untitled
Untitled
types of logic gates
Experiment No 1
rupa
