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Author : SDC
Project access type : Public
If you have any questions about this or other designs, feel free to shoot me an email at [email protected] I don't check it very often (since it's a secondary account), and you may not receive a reply for around a week.
A simple computer with an added RAM module. A work in progress, with much more I want to add, such as bitwise operators, a larger bus size, data type support including unsigned and signed integers, floating point numbers, conditional instructions, and more. There are two programmed versions, one that calculates the fibonacci sequence, and the other uses conditional instructions to determine whether it should increment a number, or halt the program. And there is also the first design I've made, which has a lot of unneeded parts in it.
UPDATE 1: added a jump instruction to allow loops and other useful applications.
UPDATE 2: Made a second version of the design, and made a better instruction set for it, removed the Memory register, since it's totally unnecessary with a RAM module. The second version also calculates the Fib sequence.
UPDATE 3: Added signed integer addition and subtraction support to version 2. Of course, this limits the positive range of integers to 127, rather than 255, but c'est la vie, I'm going to expand the size of the bus anyway.
UPDATE 4: Version 2 is temporarily down, since I'm finally adding bitwise operator functions to the ALU.
UPDATE 5: Version 2 is now back in action, with some added functions such as increment and decrement by 1, as well as left bit shifting. The ALU still needs some more work, since I'm having trouble implementing a right bit shift function. Once I have bit shifting working, I might make a program that can multiply using the shift/add method.
UPDATE 6: Version 2 now has magnitude comparison and bit-shifting functions. Conditional jumps still in the works.
UPDATE 7: Version 2 finally has a conditional jump register. It can be loaded with a Boolean from either RAM or the ALU, or directly set to either 1 or 0 by way of a set instruction. I still need to add a flag register to the design, so it can detect overflows (and maybe in the future, interrupts).
BONUS UPDATE: After a few months of studying processor and computer design, I discovered that I've unwittingly designed a Von-Neumann architecture computer (as opposed to the Harvard architecture. Reference Wikipedia if these terms are unfamiliar). Frankly, I went into this project relatively blind, and just a week ago discovered that this kind of design had a name. Well, the more you know.
UPDATE 8: I've created a new CPU design, some of which I will implement into this main circuit later this summer. Here's the link to that design: https://circuitverse.org/users/3464/projects/19687. Also, I plan to overhaul the entire design to minimize cycle inefficiencies.