Experiment 1
Experiment 1
S Nithya /EX.No 1 Verification of logic gates and Boolean theorems
S Nithya /EX.No 1 Verification of logic gates and Boolean theoremsVerification of Logic gates and boolean theorems
digital
digital
Basics
Basics
FLIP FLOP
FLIP FLOP
Exp 1
Exp 1Logic gates
Gates using Universal NAND gate
Gates using Universal NAND gate
Workshop3
Workshop3template for using basic logic gates
Logic_Gates
Logic_Gates
Logic_Gates
Logic_Gates
Logic gates, half- full adder, half & full subtractor and MUXs
Logic gates, half- full adder, half & full subtractor and MUXsAssignment 1:
1) All logic gates with their truth tables
2) 1-bit half-adder
3) 1-bit full-adder using half-adder as module instance
4) 1-bit full-adder using gates alone
5) 1-bit half-subtractor
6) 1-bit full-subtractor using half subtractor
7) 1-bit full-subtractor using gates alone
8) 2 x 1 MUX
9) 4X1 MUX using 2X1 MUX
10) 8X1 MUX using 2X1 MUX
Earthquake Warning System
Earthquake Warning SystemThese Logic Diagram Projects are being created solely for academic purposes, in partial fulfillment of the subject of Logic Circuits and Design.
Jeet experiment 1 ECE
Jeet experiment 1 ECE
Level=1
Level=1
Nand Logic Gates
Nand Logic GatesNand logic gates obviously
Experiment 1
Experiment 1
Experiment 1
Experiment 1
Experiment 1
Experiment 1
Verefication of logic gates
Verefication of logic gatesTo know about logic gates
Verification of logic gates
Verification of logic gates
LOGIC GATES
LOGIC GATES
kalpana ECE LAB
kalpana ECE LAB
third experment
third expermentgates
