project.name

Shakil Ahmed

Member since: 1 year

Educational Institution: Brac University

Country: Bangladesh

1 to 8 DEMUX

1 to 8 DEMUX
Public
1 to 8 DEMUX

w’x’y + y’z + (x+z’)

w’x’y + y’z + (x+z’)
Public
w’x’y + y’z + (x+z’)

NOT GATE Using NAND GATE

NOT GATE Using NAND GATE
Public
NOT GATE Using NAND GATE

AND GATE Using NOR GATE

AND GATE Using NOR GATE
Public
AND GATE Using NOR GATE

And Gate by NAND GATE

And Gate by NAND GATE
Public
And Gate by NAND GATE

OR Gate Using Nand Gate

OR Gate Using Nand Gate
Public
OR Gate Using Nand Gate

8:1 MUX USING TWO 4:1 MUXs

8:1 MUX USING TWO 4:1 MUXs
Public
8:1 MUX USING TWO 4:1 MUXs

XNOR Gate

XNOR Gate
Public
XNOR Gate

A+4 and A-4 according to even odd

A+4 and A-4 according to even odd
Public
A+4 and A-4 according to even odd

10 person voting system

10 person voting system
Public
10 person voting system

BCD To 7 Segment Display

BCD To 7 Segment Display
Public
BCD To 7 Segment Display

(B'+A'C)' Using Nand Gate And Nor Gate

(B'+A'C)' Using Nand Gate And Nor Gate
Public
(B'+A'C)' Using Nand Gate And Nor Gate

1 to 8 DEMUX

1 to 8 DEMUX
Public
1 to 8 DEMUX

lab_3

lab_3
Public
lab_3

Flip-Flops using NAND Gate

Flip-Flops using NAND Gate
Public
Flip-Flops using NAND Gate

OR GATE Using NOR GATE

OR GATE Using NOR GATE
Public
OR GATE Using NOR GATE

3:8 Decoder

3:8 Decoder
Public
3:8 Decoder

2:4 Decoder

2:4 Decoder
Public
2:4 Decoder

Design an Excess 3 to BCD system using necessary parallel adder(s).

Design an Excess 3 to BCD system using necessary parallel adder(s).
Public
Design an Excess 3 to BCD system using necessary parallel adder(s).

Design a BCD to excess 5 system using necessary parallel adder(s).

Design a BCD to excess 5 system using necessary parallel adder(s).
Public
Design a BCD to excess 5 system using necessary parallel adder(s).

Design a 13 people voting system using necessary parallel and full adder(s)

Design a 13 people voting system using necessary parallel and full adder(s)
Public
Design a 13 people voting system using necessary parallel and full adder(s)

lab_3

lab_3
Public
lab_3

4x16 decoder

4x16 decoder
Public
4x16 decoder

Priority Encoder Even Odd

Priority Encoder Even Odd
Public
Priority Encoder Even Odd
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