This is a "**BCD To Seven Segment Decoder**" made using Basic Logic Gates ( AND, OR, NOT ).

The purpose of this lab experience is for the student to design and implement combinatorial logic that will decode a 4-bit BCD input to a seven segment LED display. A good understanding of BCD (Binary Coded Decimal) should also result.

4-bit binary to BCD converter

Hello,

I have built a fully working
converter that converts **16-bit binary code to BCD**.

I wanted a mode with a small amount
of gates instead of millions of cells connected in series to ROM. As a result,
I designed the converter in a slightly different way, using **only 5 ROM cells**,
one register, one shift register and, of course, since this is an algorithm
where the operation is performed by cyclically changing one piece of data, we
also need a control unit. This is only for clock control and a few minor
details.

This conversion method is generally
referred to as **double-dabble**, also known as **shift-and-add-3**. In fact, it is a
large number of ROM cells, each cell handling a 4-bit or BCD code. It works by
adding 3 to all numbers greater than or equal to 5, then shifting the entire
range of bits to the left once. This cycle is repeated as many times as the
length of the input bits, for example we have 8 bits and the cycle will be
repeated eight times.

The main difference between my converter and the others is that mine is done by a clock that is constantly blinking, and drives the cyclical circulation of a piece of data continuously across exactly the same pair of cells. This method reduces the number of gates, but may be slightly slower and more complicated. While other circuits are mostly built with series connected ROM cells and this results in a simple circuit but a higher gate count compared to mine.

Below I have attached an image of one ROM cell that converts binary code to BCD. There is also a table that describes the behaviour of this cell perfectly.

I hope you like the plan. I hope you enjoy the experience.