Dans ce projet, je construit quelques circuits logiques séquentiels:
A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This feedback selectively enables one of the two set/reset inputs so that they cannot both carry an active signal to the multivibrator circuit, thus eliminating the invalid condition.
Flip Flop Using NAND GATE
SR, JK, D, T Flip Flop
rs and jk flip flop using nand gate.
Original CircuitVerse JK Flip Flop had a bug that sometimes after J=1, K=1, if you tried to get J=0, K=0 it would invert the value instead of keeping it, as would it be expected. This can be avoided by using a T Flip Flop and finite state machine logic to make the JK Flip Flop.
Contador de Rizo Asíncrono MOD-14
Contador de Rizo MOD-14 BINARIO
This demonstrate the JK-Flipflop.
J 0, K 0 => do nothing
J 1, K 0 => Set (Q = 1, Q' = 0)
J 0, K 1 => Reset (Q = 0, Q' = 1)
J 1, K 1 => Toggle Q and Q'