Searched Projects

Franko Franić, Vježba 5

Digital Sequential circuits

RS, JK, D, T

Shift Registers (SISO, SIPO, PISO, PIPO)

Counters (Asynchronous and Synchronous)

Counters with Shift Registers (RING counter, JOHNSON's counter)

Experiment No 11 b: JK flip flop using 4x1 MUX.

Done by: 

Saranga K. Mahanta

Scholar Id: 18-14-038

Dans ce projet, je construit quelques circuits logiques séquentiels:

• Bascule RS
• Bascule RSH (syncnhrone)
• Bascule D
• Bascule D synchrone
  
• Bascule JK
• Bascule K=JK synchrone
• Bascule D flipflop
• Registre
  

A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This feedback selectively enables one of the two set/reset inputs so that they cannot both carry an active signal to the multivibrator circuit, thus eliminating the invalid condition.

Flip Flop Using NAND GATE

SR, JK, D, T Flip Flop 

rs and jk flip flop using nand gate.

3 Stage counter that counts from 0 to 7

Original CircuitVerse JK Flip Flop had a bug that sometimes after J=1, K=1, if you tried to get J=0, K=0 it would  invert the value instead of keeping it, as would it be expected. This can be avoided by using a T Flip Flop and finite state machine logic to make the JK Flip Flop.

Contador de Rizo Asíncrono MOD-14

Contador de Rizo MOD-14 BINARIO

This demonstrate the JK-Flipflop.

J 0, K 0 => do nothing
J 1, K 0 => Set (Q = 1, Q' = 0)
J 0, K 1 => Reset (Q = 0, Q' = 1)
J 1, K 1 => Toggle Q and Q'

A collection of different JK Flip Flop Circuits. If you're finding this from the CDA Computer Org review the Basic JK Flip Flop is the circuit we learned about in class.

(See this Stack Exchange post for more info https://electronics.stackexchange.com/questions/491352/jk-latch-possible-ben-eater-error/491439#491439)