project.name

Vivek Kumar

Member since: 3 years

Educational Institution: GLA UNIVERSITY MATHURA

Country: India

2 BIT SYSCHRONOUS COUNTER

2 BIT SYSCHRONOUS COUNTER
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Shift Register

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Untitled

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BCD COUNTER

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FULL-ADDER

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HALF SUBSTRACTOR

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Verification of gates

Verification of gates
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UNIVERSAL GATES

UNIVERSAL GATES
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mod 5 COUNTER

mod 5 COUNTER
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Seven hex` display

Seven hex` display
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FULL SUBSTRACTOR

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