project.name

Ujjwal Kar

Member since: 876 days

Educational Institution: Bengal Institute of Technology

Country: India

Full Adder and Subtractor using Half

Full Adder and Subtractor using Half
Public
Full Adder and Subtractor using Half

Half Adder Half Subtractor

Half Adder Half Subtractor
Public
Half Adder Half Subtractor

Multiplexer

Multiplexer
Public
Multiplexer

Untitled

Untitled
Public
Untitled

BCD Adder

BCD Adder
Public
BCD Adder

multx

multx
Public
multx

HALF ADDER AND HALF SUBTRACTORR

HALF ADDER AND HALF SUBTRACTORR
Public
HALF ADDER AND HALF SUBTRACTORR

ALU

ALU
Public
ALU

ALU

ALU
Public
ALU

4 bit Adder-subtractor unit

4 bit Adder-subtractor unit
Public
4 bit Adder-subtractor unit

Design and simulate a 4 input decrementer circuit.

Design and simulate a 4 input decrementer circuit.
Public
Design and simulate a 4 input decrementer circuit.

ALU

ALU
Public
ALU

Design and Realiization of Basic Logic gates

Design and Realiization of Basic Logic gates
Public
Design and Realiization of Basic Logic gates

Cascade two 4:1 Multiplexers to implement an 8:1 Mux.

Cascade two 4:1 Multiplexers to implement an 8:1 Mux.
Public
Cascade two 4:1 Multiplexers to implement an 8:1 Mux.
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