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Multiplexers

Multiplexer

For a decoder, If the input is a N bit binary number, then the output will be one the lines of the 2^N output lines.

So, for a 2-bit binary input, there will be 2^2 output lines and only one of the output lines will be active according to the binary combination of the inputs. This type of decoder is known as 2 to 4 decoder.

A

B

Q0

Q1

Q2

Q4

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

1

1

1

0

0

0

1

Consider a 8:1 multiplexer that takes 8 two-bit inputs (T8 to T1), three-bit control signal (S) and has an output (Out). This Type of multiplexer is known as a 8 to 1 multiplexer. The truth table is given below:

S2

S1

S0

OUT

0

0

0

T1

0

0

1

T2

0

1

0

T3

0

1

1

T4

1

0

0

T5

1

0

1

T6

1

1

0

T7

1

1

1

T8

This is a circuit design for 4:1 Multiplexer

Coursework for CPE111 course.

Fork the project to test the circuit.

Coursework for CPE111.

Fork the project to test the circuit.

Multiplexer made from NOT and 2-Input OR gates

Instructions

Set both buttons to off (RED). Now reset the sequencer and turn on button 1 and 2 (set to GREEN). 

Button 1 controls the data fed to the displays.

OFF = Clear all displays ON = Programmed message

Button 2 controls the clock.

To change the message, dump the core or reset the EEPROM and rewrite the suitable data for the 16-Segment Displays. If the new message contains lesser or more letters/numbers to show, make suitable changes to the Sequencer and change the number of displays used.

Abdul Muthalib

Roll no: 2

Reg no: 20919002

4-1 Multiplexer

4-input

2-data selector

1-data channel (output)

Implementation of a MUX using Basic Gates

Classification of Combinational circuit

Multiplexer - It is a combinational digital circuit that forward data from one of the 2ⁿ input lines to a single output line on the base of n selection lines.

D.L.F experiment 03(d) 

Minesweeper: The game

Class lab project

4:1 MUX

This circuit demonstrates a way to simplify the given boolean expression using multiplexers.

A little experiment of mine where I have a crap ton of digital logic stuff. Below I'll just have the whole list

• Half & Full Adders
• Half & Full Subtractors
• 4 Bit Parallel Adders & Subtractors
• 1, 2, 4 & 8 bit comparators
• Encoders & Decoders
• Latches & Flip Flops
• Multiplexer

Multiplexer lol

4-bit Multiplexer implemented in NAND gates (both 3-input and 2-input) 

4-bit Multiplexer implemented in 2-input NAND gates.

This is a demonstration of a multiplexer (MUX) performing complex multiply-accumulate (MAC) operations in the Stochastic Computing (SC) domain, dubbed multiplexer multiply-accumulate (MMAC) architecture for accelerating neural network (NN) on the hardware level.

SC is an unconventional computing method, representing information as a bitstream of a probability distribution. That in turn allows a simple AND gate to execute arithmetic multiplication because in probability, P(A n B) = P(A) & P(B), provided that both bitstreams A and B are not correlated.

There are two random number sources, i.e. Sobol Sequence Generator and the linear feedback shift register (LFSR) Generator. Sobol sequence is used for input pixel MUX-based stochastic number generator (SNG), while LFSR is used for the NN weight MUX SNGs. The weights have one byte less than the input pixel because the weights had been encoded in the probability domain. The LFSR is shared via permutation and clock-shifting methods. The clock-shifting method is achieved via shift registers, although it is not being used in this simulation. The LFSR has to be initialized with a seed, which could be done with the reset button.

The MAC result is accumulated over time at the last counter. The actual weights of the NN are retrieved via comparator and counter to check whether the weight converged to the actual value. Although there could be errors in the weights, the final MAC value did not budge, showcasing the error resiliency of the SC system.

MUX is known to function for signal rerouting in modern digital electronics. However, it could perform arithmetic addition in the SC domain. Even more bizarre, according to the latest finding, it could perform MAC operation if designed correctly, overturning the usual understanding of digital fundamentals. In short, SC can push digital electronics beyond the limit of boolean logic. All you have to do is to represent the information as probability.

Visit my work for more details related to SC.
https://spj.science.org/doi/10.34133/research.0307