Full Adder

Clocked sequential circuit(exp-16)Akashdeep

J/K Flip Flop(Akashdeep)

2-bit Arithmetic Logic Unit(Internal Assessment)

Binary Mutiplier 3*3 (Akashdeep)

Experiment - 3 Adder M=0

Half adder

Decoder (2 to 4) Akashdeep

D Latch Using NAND(Akashdeep)

ALU Design 8-bit(Akashdeep)

Half Subtractor

T Flip Flop(Akashdeep)

Encode ( 4 to 2 ) Akashdeep

1x4 Demultiplexer( Akashdeep )

NOR Latch(Akashdeep)

Binary Multiplier (Akashdeep)

Exp 4 Carry look-ahead adder

sub M=0 Exp - 3

SR Latch Using NOR(Akashdeep)

Adder M=1 Exp - 3

Encoder ( 8 to 3) Akashdeep

NAND Latch(Akashdeep)

4x1 Multiplexer (Akashdeep)

Decode (3 to 8) Akashdeep

Master Slave D Flip flop(Akashdeep)

SR Latch Using NAND(Akashdeep)

1x8 Demutliplexer( Akashdeep )

Binary to Gray code (exp - 5)

logic gates

Sequential Circuit using JK Flip Flop

8x1 Multiplexer (Akashdeep)

Full Subtractor

Sequential Circuit using D Flip Flop(Akashdeep)

Gray to Binay Code (exp - 5)

sub M=1 exp - 3

D Latch Using NOR(Akashdeep)

Sequential Circuit using D Flip Flop(Akashdeep)

JK uisng D flip flop(Akashdeep)

ALU Design 2-bit(Akashdeep)