project.name

Ayush Raj

Member since: 2 years

Educational Institution: Not Entered

Country: Not Entered

practical lab exam

practical lab exam
Public
practical lab exam

Logic Gates

Logic Gates
Public
Logic Gates

HALF ADDER

HALF ADDER
Public
HALF ADDER

And gate

And gate
Public
And gate

XNOR gate

XNOR gate
Public
XNOR gate

AND gate

AND gate
Public
AND gate

AND gate

AND gate
Public
AND gate

OR gate

OR gate
Public
OR gate

NOT gate

NOT gate
Public
NOT gate

XOR gate

XOR gate
Public
XOR gate

full adder

full adder
Public
full adder

Untitled

Untitled
Public
Untitled

HALF ADDER

HALF ADDER
Public
HALF ADDER

full subtractor using half subtractor

full subtractor using half subtractor
Public
full subtractor using half subtractor

HALF SUBTRACTOR

HALF SUBTRACTOR
Public
HALF SUBTRACTOR

MULTIPLEXER AND LOGICAL UNIT

MULTIPLEXER AND LOGICAL UNIT
Public
MULTIPLEXER AND LOGICAL UNIT

AND gate

AND gate
Public
AND gate

AND gate

AND gate
Public
AND gate

full subtractor

full subtractor
Public
full subtractor

2:1 MULTIPLEXER

2:1 MULTIPLEXER
Public
2:1 MULTIPLEXER

4-BIT BCD ADDER

4-BIT BCD ADDER
Public
4-BIT BCD ADDER

Untitled

Untitled
Public
Untitled

NOR gate

NOR gate
Public
NOR gate

full adder using half adder

full adder using half adder
Public
full adder using half adder

NAND

NAND
Public
NAND

4 INPUT DECREMENTER CIRCUIT

4 INPUT DECREMENTER CIRCUIT
Public
4 INPUT DECREMENTER CIRCUIT
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