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Ayush Raj

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

practical lab exam

practical lab exam
Public
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Logic Gates

Logic Gates
Public
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HALF ADDER

HALF ADDER
Public
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And gate

And gate
Public
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XNOR gate

XNOR gate
Public
project.name

AND gate

AND gate
Public
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AND gate

AND gate
Public
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OR gate

OR gate
Public
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NOT gate

NOT gate
Public
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XOR gate

XOR gate
Public
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full adder

full adder
Public
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Untitled

Untitled
Public
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HALF ADDER

HALF ADDER
Public
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HALF SUBTRACTOR

HALF SUBTRACTOR
Public
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MULTIPLEXER AND LOGICAL UNIT

MULTIPLEXER AND LOGICAL UNIT
Public
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AND gate

AND gate
Public
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AND gate

AND gate
Public
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full subtractor

full subtractor
Public
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2:1 MULTIPLEXER

2:1 MULTIPLEXER
Public
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4-BIT BCD ADDER

4-BIT BCD ADDER
Public
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Untitled

Untitled
Public
project.name

NOR gate

NOR gate
Public
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full adder using half adder

full adder using half adder
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NAND

NAND
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4 INPUT DECREMENTER CIRCUIT

4 INPUT DECREMENTER CIRCUIT
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full subtractor using half subtractor

full subtractor using half subtractor
Public
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