project.name

Ayush Raj

Member since: 113 days

Educational Institution:

Country: Not Entered

HALF ADDER

HALF ADDER
Public
HALF ADDER

HALF SUBTRACTOR

HALF SUBTRACTOR
Public
HALF SUBTRACTOR

AND gate

AND gate
Public
AND gate

AND gate

AND gate
Public
AND gate

AND gate

AND gate
Public
AND gate

AND gate

AND gate
Public
AND gate

Logic Gates

Logic Gates
Public
Logic Gates

OR gate

OR gate
Public
OR gate

Untitled

Untitled
Public
Untitled

NOT gate

NOT gate
Public
NOT gate

NAND

NAND
Public
NAND

XNOR gate

XNOR gate
Public
XNOR gate

NOR gate

NOR gate
Public
NOR gate

XOR gate

XOR gate
Public
XOR gate

Untitled

Untitled
Public
Untitled

full adder using half adder

full adder using half adder
Public
full adder using half adder

full subtractor using half subtractor

full subtractor using half subtractor
Public
full subtractor using half subtractor

full adder

full adder
Public
full adder

full subtractor

full subtractor
Public
full subtractor

4 INPUT DECREMENTER CIRCUIT

4 INPUT DECREMENTER CIRCUIT
Public
4 INPUT DECREMENTER CIRCUIT

practical lab exam

practical lab exam
Public
practical lab exam

HALF ADDER

HALF ADDER
Public
HALF ADDER

And gate

And gate
Public
And gate

2:1 MULTIPLEXER

2:1 MULTIPLEXER
Public
2:1 MULTIPLEXER

MULTIPLEXER AND LOGICAL UNIT

MULTIPLEXER AND LOGICAL UNIT
Public
MULTIPLEXER AND LOGICAL UNIT

4-BIT BCD ADDER

4-BIT BCD ADDER
Public
4-BIT BCD ADDER
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Ayush Raj is not a collaborator of any project.