project.name

Asad Ur Rehman ELE Kohat Batch 22

Member since: 1 year

Educational Institution: University Of Engineering And Technology Peshawar

Country: Pakistan

AND Gate

AND Gate
Public
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Nand Gate

Nand Gate
Public
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Nor gate display

Nor gate display
Public
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CIRCUIT FOR PRODUCT OF SUM POS FORM

CIRCUIT FOR PRODUCT OF SUM POS FORM
Public
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SR LATCH

SR LATCH
Public
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D FLIP-FLOP

D FLIP-FLOP
Public
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LAB NO 6 (POS)

LAB NO 6 (POS)
Public
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Karnaugh Map

Karnaugh Map
Public
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Simplified

Simplified
Public
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UnSimplified

UnSimplified
Public
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LAB # 04

LAB # 04
Public
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CIRCIUT FOR PRODUCT OF SUM (POS)

CIRCIUT FOR PRODUCT OF SUM (POS)
Public
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TASK : 4 (D-Flip flop 4 bit shift-register)

TASK : 4 (D-Flip flop 4 bit shift-register)
Public
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CIRCUIT FOR PRODUCT OF SUM POS FORM

CIRCUIT FOR PRODUCT OF SUM POS FORM
Public
project.name

GATES

GATES
Public
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And gate display

And gate display
Public
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OR gate display

OR gate display
Public
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Nand gate display

Nand gate display
Public
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Xnor gate display

Xnor gate display
Public
project.name

Nor gate display

Nor gate display
Public
project.name

CIRCUIT FOR PRODUCT OF SUM POS FORM

CIRCUIT FOR PRODUCT OF SUM POS FORM
Public
project.name

And gate display

And gate display
Public
project.name

8x1 multiplexer

8x1 multiplexer
Public
project.name

OR gate display

OR gate display
Public
project.name

SR LATCH

SR LATCH
Public
project.name

xor gate display

xor gate display
Public
project.name

8x1 multiplexer

8x1 multiplexer
Public
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TASK :1 (SR-LATCHES)

TASK :1 (SR-LATCHES)
Public
project.name

8x1 multiplexer by using all logic gates

8x1 multiplexer by using all logic gates
Public
project.name

LAB # 04

LAB # 04
Public
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And gate display

And gate display
Public
project.name

Gates Simulation

Gates Simulation
Public
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UnSimplified

UnSimplified
Public
project.name

xor gate

xor gate
Public
project.name

xor gate display

xor gate display
Public
project.name

Untitled

Untitled
Public
project.name

NOT gate display

NOT gate display
Public
project.name

8x1 multiplexer by using all logic gates

8x1 multiplexer by using all logic gates
Public
project.name
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