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Abhishek kumar

Member since: 3 months

Educational Institution: Not Entered

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EXPERIMENT 3

EXPERIMENT 3
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EXPERIMENT 2

EXPERIMENT 2
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ALL GATES

ALL GATES
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GATES

GATES
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Half Subtractor

Half Subtractor
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FULL adder (NAND)

FULL adder (NAND)
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FULL SUBTRACTOR USING NAND GATE

FULL SUBTRACTOR USING NAND GATE
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2-bit magnitude comparators using Nand gates

2-bit magnitude comparators using Nand gates
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1 BIT magnitude camparator

1 BIT magnitude camparator
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Magnitude Comparators 1-bit0

Magnitude Comparators 1-bit0
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2:1 MUX nad 1:2 DE-MUX

2:1 MUX nad 1:2 DE-MUX
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EXPERIMENT 4

EXPERIMENT 4
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EXPERIMENT no.7 LEVEL 1

EXPERIMENT no.7 LEVEL 1
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verification of logic gate

verification of logic gate
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EXPERIMENT 2

EXPERIMENT 2
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EXperiment 7 level-2

EXperiment 7 level-2
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EXPERIMENT 8 J-K FLIPFLOP USING NAND GATE

EXPERIMENT 8 J-K FLIPFLOP USING NAND GATE
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EXPERIMENT 8 LEVEL 2

EXPERIMENT 8 LEVEL 2
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