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Project access type: Public
[ Under Development ]
This is a 16-bit processor with 18 instructions of length 16 bit, 16 registers of size 16 bit and only the primary cache in its architecture.
[ Instruction Set ]
from 0 to f0 is also known as ra as its used for jump and link and jump registerinstructions0000 0XXX XXXX XXXX - no-op X can be anything- no operation 0000 1XXX XXXX XXXX - jmp X is the address offset from pc - jump0001 XXXX YYYY YYYY - lli X is the register to write data to and Y is the data to load in lower 8 bits- load lower imediate0010 XXXX YYYY YYYY - orui X is the register to write data to and Y is the data to or with the upper 8 bits in X - or upper imediate0011 0XXX XXXX XXXX - jal X is the address offset to pc and pc+1 is stored in ra - jump and link0011 1XXX XXXX XXXX - jr X can be anything, pc is restored by value in ra- jump register( only from ra register )0100 XXXX YYYY ZZZZ - shw X is the register containing the data to write, Y is the offset, Z is the register containing the address in memory - store 16bits in memory ( Addresses in memory can be read or written 16 bits at a time only)0101 XXXX YYYY ZZZZ - lhw X is the register to store data in, Y is the offset, Z is the register containing the memory address - load 16bits from memory ( That is 0 represents first 16 bits and 1 represents next 16 bits)0110 XXXX YYYY ZZZZ - beq X is the PC offset, Y and Z are registers to compare - break equal0111 XXXX YYYY ZZZZ - bne X is the PC offset, Y and Z are registers to compare - break not equal
In the following, assume $ is the operation
X, Y and Z are registers, X=Y$Z
1000 XXXX YYYY ZZZZ - and - and gate1001 XXXX YYYY ZZZZ - or - or gate1010 XXXX YYYY ZZZZ - add - addition1100 XXXX YYYY ZZZZ - and~ - A and ~B1101 XXXX YYYY ZZZZ - or~ - A or ~B1110 XXXX YYYY ZZZZ - sub - subtraction
if(Y<Z) X=1 else X=0
1111 XXXX YYYY ZZZZ - stl - set less than
To do list:
Forwarding unit - on going
Hazard detection unit - yet to start
Created: Nov 04, 2020
Updated: Apr 06, 2021