Member since: 3 years
Educational Institution: Techno India University kolkata
Country: India
AND from NAND
AND from NANDOR from NAND
OR from NANDNOT from NAND
NOT from NANDAll Gates
All GatesAND
ANDFull Adder Using NAND gate
Full Adder Using NAND gateXNOR from NAND
XNOR from NANDOR using NOR
OR using NORFull subtractor using NAND gate
Full subtractor using NAND gateAND using NAND
AND using NANDHalf Adder
Half AdderUntitled
UntitledAND OR NOT Gate
AND OR NOT Gate1x4 Demux using 2 to 4 Decoder
1x4 Demux using 2 to 4 DecoderQ.16) Full Subtractor Implementation
Q.16) Full Subtractor ImplementationHalf Subtractor and Full Subtractor
Half Subtractor and Full SubtractorQ.15) Full adder Implementation
Q.15) Full adder ImplementationExperiment-2
Experiment-28bit Substractor
8bit SubstractorHalf Adder ,Full adder , Half Subtractor and Full Subtractor
Half Adder ,Full adder , Half Subtractor and Full SubtractorFull adder using NAND Gate
Full adder using NAND GateNOT using NOR
NOT using NORBASIC LOGIC GATES USING NOR GATE
BASIC LOGIC GATES USING NOR GATEBinary -to -Gray, Gray -to -Binary code converte
Binary -to -Gray, Gray -to -Binary code convertehalf subtractor
half subtractorFull Adder using NAND and NOR gates
Full Adder using NAND and NOR gatesH.A. using nor gate and H.A. using XOR , AND gate
H.A. using nor gate and H.A. using XOR , AND gateExperiment-2
Experiment-2