Member since: 4 years
Educational Institution: Techno India University kolkata
Country: India
AND from NAND
AND from NANDOR from NAND
OR from NANDNOT from NAND
NOT from NANDAll Gates
All GatesAND
ANDFull Adder Using NAND gate
Full Adder Using NAND gateOR using NOR
OR using NORAND using NAND
AND using NANDHalf Adder
Half AdderUntitled
UntitledAND OR NOT Gate
AND OR NOT Gate1x4 Demux using 2 to 4 Decoder
1x4 Demux using 2 to 4 DecoderQ.16) Full Subtractor Implementation
Q.16) Full Subtractor ImplementationQ.15) Full adder Implementation
Q.15) Full adder ImplementationHalf Adder ,Full adder , Half Subtractor and Full Subtractor
Half Adder ,Full adder , Half Subtractor and Full SubtractorNOT using NOR
NOT using NORBASIC LOGIC GATES USING NOR GATE
BASIC LOGIC GATES USING NOR GATE8bit Substractor
8bit SubstractorXNOR from NAND
XNOR from NANDFull subtractor using NAND gate
Full subtractor using NAND gateFull adder using NAND Gate
Full adder using NAND GateHalf Subtractor and Full Subtractor
Half Subtractor and Full SubtractorExperiment-2
Experiment-2Binary -to -Gray, Gray -to -Binary code converte
Binary -to -Gray, Gray -to -Binary code convertehalf subtractor
half subtractorH.A. using nor gate and H.A. using XOR , AND gate
H.A. using nor gate and H.A. using XOR , AND gateFull Adder using NAND and NOR gates
Full Adder using NAND and NOR gatesExperiment-2
Experiment-2