project.name

Lokesh Pandey

Member since: 676 days

Educational Institution: Not Entered

Country: Not Entered

expriment1:All logic gates

expriment1:All logic gates
Public
expriment1:All logic gates

experiement 3: full adder and substractor

experiement 3: full adder and substractor
Public
experiement 3: full adder and substractor

DECMENTER(FA)

DECMENTER(FA)
Public
DECMENTER(FA)

INCREMENTER

INCREMENTER
Public
INCREMENTER

INCREMENTER(FA)

INCREMENTER(FA)
Public
INCREMENTER(FA)

4:1 CASCADE

4:1 CASCADE
Public
4:1 CASCADE

ARITHMETIC UNIT

ARITHMETIC UNIT
Public
ARITHMETIC UNIT

COMPOSITE UNIT

COMPOSITE UNIT
Public
COMPOSITE UNIT

experiment2:half adder and substractor

experiment2:half adder and substractor
Public
experiment2:half adder and substractor

RIPPLE SUBSTRACTOR

RIPPLE SUBSTRACTOR
Public
RIPPLE SUBSTRACTOR

RIPPLE CARRY

RIPPLE CARRY
Public
RIPPLE CARRY

Experiment 4:Full adder using two half adder

Experiment 4:Full adder using two half adder
Public
Experiment 4:Full adder using two half adder

2:1 MUX CASCADE

2:1 MUX CASCADE
Public
2:1 MUX CASCADE

LOGIC UNIT and Logiic gates

LOGIC UNIT and Logiic gates
Public
LOGIC UNIT and Logiic gates

4-Bit Incrementer

4-Bit Incrementer
Public
4-Bit Incrementer

BCD

BCD
Public
BCD
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