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A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by connecting the R input through an inverter, and the S input is connected directly to data input. The modified clocked SR flip-flop is known as D-flip-flop and is shown below. From the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs are same and high. In many practical applications, these input conditions are not required. These input conditions can be avoided by making them complement of each other.

Truth Table for D flip-flop

Clk

D

Q

Q^’

0

1

Previous or memory state

0

1

1

0

0

1

1

1

1

0

This is a 2 bit counter using d flip-flops that skips 0. The sequence is 1, 2, 3, 1, 2,... .

TD1 de l'architecture des ordinateurs :  création d'un banc de registre, registre, d flip-flop...