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Logic diagrams for nand2tetris part 1 (projects 1 to 6).

Digital Combinational Circuits

Gates: NOT,  AND, OR, NAND, NOR, XOR, XNOR

half adder, full adder, multiplexer, demultiplexer

4:1 8:1 mux expansion

Circuit to left-shift an 8-bit number by 0-7 bits! :D

2:1 multiplexer

8x1 multiplexer has 8 data input lines I₀, I₁, I₂, I₃, I₄, I₅, I₆, I₇, 3 select lines S₀, S₁, S₂ and one output, Y.

Truth Table for 8x1 Multiplexer

Data Select Input

Output

Y

S₂

S₁

S₀

0

0

0

I₀

0

0

1

I₁

0

1

0

I₂

0

1

1

I₃

1

0

0

I₄

1

0

1

I₅

1

1

0

I₆

1

1

1

I₇

Design multiplexer using basic gates,

Boolean function implementation

dcd_task3

task3

task3

task3

Implementación de un multiplexor 2×1

Implementación de un multiplexores nx1

multiplexador 4x1 utilizando portas logicas

Group 5 - CAO 

CpE-3302

4-Bit adder with memory Control

Practice for creating and instantiating sub-circuits into a larger circuit, includes gate logic for some circuits like 2-to-1 mux and 3-to-8 decoder, as well as bit-to-bus combiner and FSM logic using T flip-flops.

ROM-instructed sequence taking data in and using half of the bits to perform memory storage and selection functions.

just playing around with things