Exp-6

Logic gates

InternalAssessment-3bit-Arraymultiplier

Exp-6

exp 10 (a)

controlledLathes2

exp 11(a)

Logic gates

Logic gates

experiment-4

Rightshift

Full adder using XOR

practicalcoa

Controlled Latches

Clocked sequential circuit

exp14(b)

exp8 (a)

K-MAP

Controlled latches

experiment-5

logic gate -2

exp 9 (b)

exp16

EXP 12 T FLIP FLOP

Untitled

experiment-5

exp 8(c)

half adder

experiment7(c)

Jk flipflop

Universal(c)

Logic gates-3

exp 6(b)

exp7(a)

exp 4

exp 8 (b)

Alu circuit design exp 13(b)

Exp 9 (a)

InternalAssessment-2*2 array Multiplier

Master slave D flip flop

exp7(a)

Exp 12 JKflipflop

Rightshift

exp 10 (b)

Leftshift

ALU circuit design(a)