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Exp-6
Exp-6Exp-6
Exp-6experiment-4
experiment-4Full adder using XOR
Full adder using XORpracticalcoa
practicalcoaControlled Latches
Controlled LatchesClocked sequential circuit
Clocked sequential circuitexp14(b)
exp14(b)exp8 (a)
exp8 (a)K-MAP
K-MAPControlled latches
Controlled latchesexperiment-5
experiment-5Logic gates
Logic gateslogic gate -2
logic gate -2exp16
exp16exp 10 (a)
exp 10 (a)experiment-5
experiment-5Untitled
Untitledhalf adder
half adderJk flipflop
Jk flipflopUniversal(c)
Universal(c)exp 6(b)
exp 6(b)exp 11(a)
exp 11(a)Exp 9 (a)
Exp 9 (a)InternalAssessment-2*2 array Multiplier
InternalAssessment-2*2 array MultiplierMaster slave D flip flop
Master slave D flip flopexp7(a)
exp7(a)Exp 12 JKflipflop
Exp 12 JKflipflopRightshift
Rightshiftexp 10 (b)
exp 10 (b)Leftshift
LeftshiftALU circuit design(a)
ALU circuit design(a)Rightshift
Rightshiftexp 9 (b)
exp 9 (b)Logic gates
Logic gatesInternalAssessment-3bit-Arraymultiplier
InternalAssessment-3bit-ArraymultiplierEXP 12 T FLIP FLOP
EXP 12 T FLIP FLOPexp 4
exp 4controlledLathes2
controlledLathes2Logic gates
Logic gatesexp7(a)
exp7(a)Alu circuit design exp 13(b)
Alu circuit design exp 13(b)exp 8(c)
exp 8(c)exp 8 (b)
exp 8 (b)Logic gates-3
Logic gates-3experiment7(c)
experiment7(c)