Flip-Flops and Latches
Flip-Flops and LatchesMaking latches and flip-flops from basic logic components
Flip-Flops
Flip-FlopsFlip-Flops and Latches.
Tests
Testsbasic D latch
Latches
Latches
[CSCA] Latches and Flip-flops
[CSCA] Latches and Flip-flops
Latches and flip-flops as discussed in the Computer Science and Computer Architectures [CSCA] course at the University of Applied Sciences CAMPUS 02, Graz, Austria.
The project features the following circuits:
- SR Latch - demonstrates the behavior of an SR Latch. [learn more]
-
Clock - demonstrates the Clock Signal. [learn more]
- Clocked SR Latch - developed by bringing the Clock Signal to the SR Latch. [learn more]
- D Latch - demonstrates the behavior of a D Latch. [learn more]
- Clocked D Latch - developed by bringing the Clock Signal to the D Latch. [learn more]
Computer Logic
Computer LogicA little experiment of mine where I have a crap ton of digital logic stuff. Below I'll just have the whole list
- Half & Full Adders
- Half & Full Subtractors
- 4 Bit Parallel Adders & Subtractors
- 1, 2, 4 & 8 bit comparators
- Encoders & Decoders
- Latches & Flip Flops
- Multiplexer
Sequential Logic
Sequential Logic
Latch SR NAND
Latch SR NAND
Latch SR NOR
Latch SR NOR
Latch D NAND Enable
Latch D NAND Enable
Latch D NOR
Latch D NOR
Latch JK NOR
Latch JK NOR
Latch D NOR Gates
Latch D NOR Gates
Latch D Enable NAND Gates
Latch D Enable NAND Gates
Latch JK NOR Gates
Latch JK NOR Gates
Latch SR Enable NOR
Latch SR Enable NOR
Latch SR Enable NAND
Latch SR Enable NAND
Latches and Flipflops
Latches and FlipflopsProject with all the Latches and Flipflops constructed from scratch with Logic gates. With comments/explanations.
Features:
Latches: Set-Reset, Set-Reset-Toggle, Delay
Flipflops: Set-Reset, Delay, Toggle, Jump and Kill
