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Tags: Latches

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Flip-Flops and Latches

Flip-Flops and Latches
Making latches and flip-flops from basic logic components

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Basic NOR Latch

Basic NOR Latch

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Flip-Flops

Flip-Flops

Flip-Flops and Latches. 


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Tests

Tests

basic D latch


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[CSCA] Latches and Flip-flops

[CSCA] Latches and Flip-flops

Latches and flip-flops as discussed in the Computer Science and Computer Architectures [CSCA] course at the University of Applied Sciences CAMPUS 02, Graz, Austria.

The project features the following circuits:

  • SR Latch - demonstrates the behavior of an SR Latch. [learn more]
  • Clock - demonstrates the Clock Signal. [learn more]
  • Clocked SR Latch - developed by bringing the Clock Signal to the SR Latch. [learn more]
  • D Latch - demonstrates the behavior of a D Latch. [learn more]
  • Clocked D Latch - developed by bringing the Clock Signal to the D Latch. [learn more]

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A little experiment of mine where I have a crap ton of digital logic stuff. Below I'll just have the whole list

  • Half & Full Adders
  • Half & Full Subtractors
  • 4 Bit Parallel Adders & Subtractors
  • 1, 2, 4 & 8 bit comparators
  • Encoders & Decoders
  • Latches & Flip Flops
  • Multiplexer

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Sequential Logic

Sequential Logic

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Latch SR NAND

Latch SR NAND

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Latch SR NOR

Latch SR NOR

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Latch D NAND Enable

Latch D NAND Enable

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Latch D NOR

Latch D NOR

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Latch JK NOR

Latch JK NOR

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Latch D NOR Gates

Latch D NOR Gates

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Latch D Enable NAND Gates

Latch D Enable NAND Gates

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Latch JK NOR Gates

Latch JK NOR Gates

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Latch SR Enable NOR

Latch SR Enable NOR

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Latch SR Enable NAND

Latch SR Enable NAND