project.name

Kaivalya Pitale

Member since: 501 days

Educational Institution: Pune Institute of Computer Technology

Country: India

Parity Generator and Parity Checker

Parity Generator and Parity Checker
Public
Parity Generator and Parity Checker

Implementation of Boolean expression using single 8:1 MUX

Implementation of Boolean expression using single 8:1 MUX
Public
Implementation of Boolean expression using single 8:1 MUX

conversion of ff

conversion of ff
Public
conversion of ff

Asynchronous UP and Down counter

Asynchronous UP and Down counter
Public
Asynchronous UP and Down counter

Sequence detector

Sequence detector
Public
Sequence detector

Untitled

Untitled
Public
Untitled

Implementation of 2-bit comparator

Implementation of 2-bit comparator
Public
Implementation of 2-bit comparator

BCD to XS3 code converter

BCD to XS3 code converter
Public
BCD to XS3 code converter

Implement f(A,B,C,D)=(0,2,4,7,9,10,12,13,15) using IC 74153

Implement f(A,B,C,D)=(0,2,4,7,9,10,12,13,15) using IC 74153
Public
Implement f(A,B,C,D)=(0,2,4,7,9,10,12,13,15) using IC 74153

Implementation of Boolean expression using Single 4:1 MUX MSB reduction

Implementation of Boolean expression using Single 4:1 MUX MSB reduction
Public
Implementation of Boolean expression using Single 4:1 MUX MSB reduction

Even Parity Generator and Parity Checker

Even Parity Generator and Parity Checker
Public
Even Parity Generator and Parity Checker

Boolean expression realization using single 4:1 MUX using LSB reduction

Boolean expression realization using single 4:1 MUX using LSB reduction
Public
Boolean expression realization using single 4:1 MUX using LSB reduction

Boolean expression realization with 4:1 MUX using MSB reduction method

Boolean expression realization with 4:1 MUX using MSB reduction method
Public
Boolean expression realization with 4:1 MUX using MSB reduction method

Boolean expression implementation with 4:1 MUX usisng LSB reduction method

Boolean expression implementation with 4:1 MUX usisng LSB reduction method
Public
Boolean expression implementation with 4:1 MUX usisng LSB reduction method

DEMUX and Decoder

DEMUX and Decoder
Public
DEMUX and Decoder

Implement full adder and full subtractor using IC 74153 (Dual 4:1 MUX)

Implement full adder and full subtractor using IC 74153 (Dual 4:1 MUX)
Public
Implement full adder and full subtractor using IC 74153 (Dual 4:1 MUX)

3-bit binary to gray code converter using 4:1 MUX

3-bit binary to gray code converter using 4:1 MUX
Public
3-bit binary to gray code converter using 4:1 MUX

Implement 3 bit Gray to Binary code converter using 3:8 decoder.

Implement 3 bit Gray to Binary code converter using 3:8 decoder.
Public
Implement 3 bit Gray to Binary code converter using 3:8 decoder.

Implementation of Boolean expression using 8:1 MUX

Implementation of Boolean expression using 8:1 MUX
Public
Implementation of Boolean expression using 8:1 MUX

Parity Generator and Parity Checker

Parity Generator and Parity Checker
Public
Parity Generator and Parity Checker

Kaivalya 21444 implementation of 8:1 MUX using two 4:1 MUX

Kaivalya 21444 implementation of 8:1 MUX using two 4:1 MUX
Public
Kaivalya 21444 implementation of 8:1 MUX using two 4:1 MUX

Design D flip flop using IC7476

Design D flip flop using IC7476
Public
Design D flip flop using IC7476

Implementation of Decoder in boolean expressions

Implementation of Decoder in boolean expressions
Public
Implementation of Decoder in boolean expressions

Implementation of 2 bit comparators using logic gates

Implementation of 2 bit comparators using logic gates
Public
Implementation of 2 bit comparators using logic gates

Implementation of 3 bit Adder using Decoder in boolean expressions

Implementation of 3 bit Adder using Decoder in boolean expressions
Public
Implementation of 3 bit Adder using  Decoder in boolean expressions

Implementation of Boolean expression using Single 4:1 MUX LSB reduction

Implementation of Boolean expression using Single 4:1 MUX LSB reduction
Public
Implementation of Boolean expression using Single 4:1 MUX LSB reduction
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