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Prueba

Prueba
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practica1

practica1
1

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borrador1

borrador1
1

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MULTIPLEXOR 4 X 1

MULTIPLEXOR 4 X 1
1

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Circuito secuencial

Circuito secuencial
1

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distancia h

distancia h
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surc

surc
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ejercicio3.ALU

ejercicio3.ALU
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csa1

csa1
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pract1

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lat3
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Matrich
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1

1
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Store inf

Store inf
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Инфа

Инфа
1
ымсвы

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ring counter

ring counter
1
dld

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circuit 1

circuit 1
1

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louis

louis
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1

1
1

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Sprawdzian Eutk

Sprawdzian Eutk
1

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3*8

3*8
1

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Circuito caracol

Circuito caracol
1

cicuito caracol lectura 1101


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De-Morgan’s Law using two variables.

De-Morgan’s Law using two variables.
1

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TP4 -1

TP4 -1
1

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AND

AND
1

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Ayça

Ayça
1

project.name
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Experiment 1

Experiment 1
1 2a 2b 3 4a 4b 5 6 7a 7b 8 9

NIKHIL GUPTA 

1960627


project.name
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Experiment 1

Experiment 1
1

My first experiment in DE lab.


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EX3

EX3
1

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not

not
1

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1 project

1 project
1

1


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xor 1

xor 1
1

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1 Circuit

1 Circuit

XY'+(X+Y)'=A


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Entregable

Entregable

Primer entregable parcial


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janjuas project

janjuas project
1 3

project.name
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Lab1

Lab1
1

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CODE CONVERTOR

CODE CONVERTOR
1

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multiplexor

multiplexor
1

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test

test
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j

j
1

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CircuitVerse

CircuitVerse
1

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Untitled

Untitled
1

111


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NIRAJ DE

NIRAJ DE
DE 1

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lab 6

lab 6
1

project.name
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memoria

memoria
1

memoria digitales 2


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Untitled

Untitled
1

project.name
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Expt1

Expt1
1

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Activity 3

Activity 3
1 2 3 4 5

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LAB1

LAB1
1

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Logic Gates

Logic Gates
1

14 september 2021 year



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Half and Full Adder

Half and Full Adder
1

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Untitled

Untitled
1



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ACTIVITY 4

ACTIVITY 4
1

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7 sagment displays

7 sagment displays
1

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lab 1

lab 1
lab 1

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naveen

naveen
1

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Nam

Nam
1

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lOGES

lOGES
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10

10
1

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AHMED HAMODA

AHMED HAMODA
1

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13-1

13-1
13 1

13,1


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Informatik 1

Informatik 1
1

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DC Lab

DC Lab
1 2 3 4

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lab assignment

lab assignment
1

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KSA

KSA
1

project.name
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DEMORGANS LAW

DEMORGANS LAW
1

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trab final

trab final
1

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21UCS051_Exp9

21UCS051_Exp9
1

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Half Adder

Half Adder

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Half adder

Half adder

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Untitled

Untitled
#3 1

project.name
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Didier Circuito

Didier Circuito

project.name
1 Stars     44 Views

Tarea lab Sis. digitales

Tarea lab Sis. digitales
1

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20524068_Muhamad Taruna_1

20524068_Muhamad Taruna_1

project.name
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20524068_Muhamad Taruna_2

20524068_Muhamad Taruna_2

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SKILL BASED MINI PROJECT

SKILL BASED MINI PROJECT
1

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SKILL BASED NANDINI

SKILL BASED NANDINI
1

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decoder

decoder
1

project.name
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shaik munawar,20211csg0072

shaik munawar,20211csg0072

project.name
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full adder

full adder
1

project.name
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punto 1 taller 2

punto 1 taller 2
1

project.name
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2

2
1

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Michael Powell - CircuitVerse_CSX_1

Michael Powell - CircuitVerse_CSX_1
CSX 1

This circuit determines if two triangles are congruent given a set of six inputs relating the triangles' side lengths and angle measures.


project.name
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Untitled1

Untitled1
1

project.name
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Untitled

Untitled
1

project.name
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RS flipflop

RS flipflop
1

rs flipflop


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RS FLIPFLOP

RS FLIPFLOP
1

project.name
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Untitled1

Untitled1
1

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seven segment

seven segment

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Project 1

Project 1
1

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piso

piso
1

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experiment 1

experiment 1
1

project.name
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Half adder using XOR and NAND

Half adder using XOR and NAND
1

Experiment 2

Level 1



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Full adder using XOR and NAND

Full adder using XOR and NAND
1

Experiment 2

Level 1



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half subtractor using XOR and NANAD Gates

half subtractor using XOR and NANAD Gates
1

half subtractor


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Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
1 2

Experiment 1

Level 2



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20221CBD0014

20221CBD0014
1

project.name
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3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
1

Level 2



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3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
1

Level 2


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Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
1

Logic circuit of 2-to-1 Multiplexer


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20221CBD0014

20221CBD0014
1

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2 to 1 multiplexer

2 to 1 multiplexer
1

Realization of 2 to 1 MUX using basic and XOR gate


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1 to 2 DEMUX

1 to 2 DEMUX
1

DEMUX


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2 to 1 DEMUX

2 to 1 DEMUX
1

By using universal gate



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4 to 2 decoder

4 to 2 decoder
1

Encoder and Decoder logic gates


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4 to 2 Priority encoder

4 to 2 Priority encoder
1

Priority encoder


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LEVEL 2: Priority encoder

LEVEL 2: Priority encoder
1

A:2 Priority encoder


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Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
1

Experiment 5

level 1


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D to JK flip flop conversion

D to JK flip flop conversion
1

Experiment 6

Level 2


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level 2:exp 6 JK To D Flip-flop conversion

level 2:exp 6 JK To D Flip-flop conversion
1 6

JK TO D FLIP-FLOP CONVERSION


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D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
1 2 3 4

Experiment 6

Level 1


project.name
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CEA

CEA
1

project.name
0 Stars     5 Views

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7

his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent


project.name
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To study and verify logic gates

To study and verify logic gates

experiment no 1


project.name
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To study and verify logic gates

To study and verify logic gates

project.name
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mufeez project 1

mufeez project 1
1

project.name
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project.name
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Mapas K (5 bits)

Mapas K (5 bits)

project.name
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Basic gates

Basic gates
1 2 at

project.name
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Raushan Yadav

Raushan Yadav
1

complete gate project


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Untitled1

Untitled1
1

project.name
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Untitled

Untitled

project.name
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titled

titled
1

project.name
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assingment1

assingment1
1

project.name
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exp-3

exp-3
1

project.name
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Untitled

Untitled
1

first


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lab4

lab4
1 2

project.name
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lab4

lab4
2 1

project.name
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lab4

lab4
1 2

project.name
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Untitled

Untitled
1 4 7

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Untitled

Untitled
1 2

project.name
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Digitale Logik

Digitale Logik
1

project.name
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multiplexer

multiplexer
1

project.name
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1

1
1

8 segment


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Untitled

Untitled
1

project.name
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Ej 1

Ej 1
Ej 1

project.name
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1

1
1

project.name
0 Stars     1 Views
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Steve B. Badayos

Steve B. Badayos
t I n G S 1 2 h

project.name
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MATT DANIEL PEPINO

MATT DANIEL PEPINO
g H o S t Y 1 8