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User Image Moises Alberto Salazar Machaca

Prueba

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User Image Iris Rocio Curo Quispe

practica1

practica1
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User Image Iris Rocio Curo Quispe

borrador1

borrador1
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User Image Iris Rocio Curo Quispe

MULTIPLEXOR 4 X 1

MULTIPLEXOR 4 X 1
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User Image Iris Rocio Curo Quispe

Circuito secuencial

Circuito secuencial
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User Image Iris Rocio Curo Quispe

distancia h

distancia h
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surc

surc
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User Image Harshit Agarwal

HARSHIT

HARSHIT
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1
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ejercicio3.ALU

ejercicio3.ALU
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csa1

csa1
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User Image дмитрий красножен

pract1

pract1
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lat3

lat3
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Matrich

Matrich
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1

1
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Store inf

Store inf
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User Image Илья Да так-то

Инфа

Инфа
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ымсвы
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User Image Mishi Shah

ring counter

ring counter
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dld
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circuit 1

circuit 1
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project.name
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louis

louis
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project.name
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1

1
1
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project.name
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User Image Szymon Zacharow

Sprawdzian Eutk

Sprawdzian Eutk
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User Image سوير ال رشيد

3*8

3*8
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project.name
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User Image Yefry Sajquiy

Circuito caracol

Circuito caracol
1
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cicuito caracol lectura 1101

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User Image Anfas Walker

De-Morgan’s Law using two variables.

De-Morgan’s Law using two variables.
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project.name
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TP4 -1

TP4 -1
1
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project.name
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User Image sergio galindo

AND

AND
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Ayça

Ayça
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project.name
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User Image 1960627 NIKHIL GUPTA

Experiment 1

Experiment 1
1 2a 2b 3 4a 4b 5 6 7a 7b 8 9
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NIKHIL GUPTA 

1960627

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User Image Sharun E Rajeev

Experiment 1

Experiment 1
1
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My first experiment in DE lab.

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User Image RUAAYAH

EX3

EX3
1
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project.name
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User Image LUCAS HENRIQUE MANHANI

not

not
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1 project

1 project
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1

project.name
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User Image saurabh kumar

xor 1

xor 1
1
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[email protected]

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User Image Nanditha AM

1 Circuit

1 Circuit
1 circuit
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XY'+(X+Y)'=A

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User Image Stephany Merari Fuentes Sierra

Entregable

Entregable
Entregable 1
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Primer entregable parcial

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janjuas project

janjuas project
1 3
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project.name
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User Image Chitanu Victor

Lab1

Lab1
1
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project.name
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User Image Chennuru sai sadvika reddy 4018

CODE CONVERTOR

CODE CONVERTOR
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multiplexor

multiplexor
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project.name
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User Image Avinash Saroj

test

test
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project.name
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j

j
1
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project.name
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User Image Erik

CircuitVerse

CircuitVerse
1
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User Image НeIzVeStn0sTb

Untitled

Untitled
1
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111

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User Image niraj kumar

NIRAJ DE

NIRAJ DE
DE 1
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lab 6

lab 6
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project.name
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User Image Christian Alejandro Sarmiento Sánchez

memoria

memoria
1
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memoria digitales 2

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User Image Miguel Ángel Medina Arellanes

Untitled

Untitled
1
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User Image HRISHIK SANCHETI

Expt1

Expt1
1
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User Image Adrian Tuazon

Activity 3

Activity 3
1 2 3 4 5
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User Image Diyora Botirova

LAB1

LAB1
1
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User Image Khadichabonu

Logic Gates

Logic Gates
1
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14 september 2021 year


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User Image Abhinav

Half and Full Adder

Half and Full Adder
1
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project.name
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User Image Akash Dubey

Untitled

Untitled
1
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project.name
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User Image Christopher Fernand0

ACTIVITY 4

ACTIVITY 4
1
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project.name
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User Image syed Izhar Ali

7 sagment displays

7 sagment displays
1
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lab 1

lab 1
lab 1
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project.name
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naveen

naveen
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project.name
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User Image Nam Ngô Hoài

Nam

Nam
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project.name
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lOGES

lOGES
1
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project.name
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User Image asif khan

10

10
1
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project.name
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User Image Ahmed hamoda l Ali marey

AHMED HAMODA

AHMED HAMODA
1
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project.name
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User Image Keenan

13-1

13-1
13 1
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13,1

project.name
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User Image Hoara

Informatik 1

Informatik 1
1
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project.name
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User Image Tarun Bansal

DC Lab

DC Lab
1 2 3 4
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project.name
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User Image 20bcs011 Hitesh vashisth

lab assignment

lab assignment
1
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project.name
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KSA

KSA
1
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project.name
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User Image YANALA ABHINAY REDDY

DEMORGANS LAW

DEMORGANS LAW
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project.name
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User Image Piero

trab final

trab final
1
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project.name
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User Image Chirag

21UCS051_Exp9

21UCS051_Exp9
1
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project.name
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User Image Nath pushkar

Half Adder

Half Adder
Half adder 1
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project.name
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User Image Nath pushkar

Half adder

Half adder
Half adder 1
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project.name
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User Image Alp Tuğrul Akşam

Untitled

Untitled
#3 1
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project.name
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User Image Didier Mtz Rdz

Didier Circuito

Didier Circuito
Circuito 1
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project.name
1 Stars     56 Views
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User Image Daniel Mamani Ramos

Tarea lab Sis. digitales

Tarea lab Sis. digitales
1
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project.name
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User Image Muhamad Taruna Pramudhita

20524068_Muhamad Taruna_1

20524068_Muhamad Taruna_1
SISDIG 1
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project.name
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User Image Muhamad Taruna Pramudhita

20524068_Muhamad Taruna_2

20524068_Muhamad Taruna_2
SISDIG 1
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project.name
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User Image vikashsharma

SKILL BASED MINI PROJECT

SKILL BASED MINI PROJECT
1
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project.name
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User Image vikashsharma

SKILL BASED NANDINI

SKILL BASED NANDINI
1
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project.name
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User Image Abdul Wahid

decoder

decoder
1
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project.name
0 Stars     65 Views
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User Image shaik munawar

shaik munawar,20211csg0072

shaik munawar,20211csg0072
experiment 1
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project.name
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User Image Pragya Mittal

full adder

full adder
1
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project.name
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User Image Jeisson fabian Torres contreras

punto 1 taller 2

punto 1 taller 2
1
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project.name
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User Image Andre Magtibay

2

2
1
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project.name
0 Stars     20 Views
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User Image Michael Powell

Michael Powell - CircuitVerse_CSX_1

Michael Powell - CircuitVerse_CSX_1
CSX 1
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This circuit determines if two triangles are congruent given a set of six inputs relating the triangles' side lengths and angle measures.

project.name
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User Image muneeraibraheem

Untitled1

Untitled1
1
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project.name
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User Image 吳尚哲

Untitled

Untitled
1
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project.name
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User Image 727821TUEC122 MONIKA SRI B.

RS flipflop

RS flipflop
1
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rs flipflop

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User Image 727821TUEC124 NANDITHA V.

RS FLIPFLOP

RS FLIPFLOP
1
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project.name
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User Image Mustafa Can Buyuksari

Untitled1

Untitled1
1
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project.name
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User Image TelAviv

seven segment

seven segment
logic 1
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project.name
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User Image Peyton McCarrick

Project 1

Project 1
1
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project.name
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User Image arpit pandey

piso

piso
1
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project.name
0 Stars     13 Views
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User Image Navya Arveti

experiment 1

experiment 1
1
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project.name
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User Image Dhrithi

Half adder using XOR and NAND

Half adder using XOR and NAND
1
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Experiment 2

Level 1


project.name
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User Image Dhrithi

Full adder using XOR and NAND

Full adder using XOR and NAND
1
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Experiment 2

Level 1


project.name
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User Image Rakshitha

half subtractor using XOR and NANAD Gates

half subtractor using XOR and NANAD Gates
1
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half subtractor

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User:
User Image Dhrithi

Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
1 2
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Experiment 1

Level 2


project.name
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User:
User Image PAVANI AMMU

20221CBD0014

20221CBD0014
1
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project.name
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User:
User Image Dhrithi

3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
1
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Level 2


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User Image Dhrithi

3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
1
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Level 2

project.name
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User:
User Image Dhrithi

Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
1
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Logic circuit of 2-to-1 Multiplexer

project.name
0 Stars     13 Views
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User Image PAVANI AMMU

20221CBD0014

20221CBD0014
1
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project.name
0 Stars     21 Views
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User Image Dhrithi

2 to 1 multiplexer

2 to 1 multiplexer
1
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Realization of 2 to 1 MUX using basic and XOR gate

project.name
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User Image Dhrithi

1 to 2 DEMUX

1 to 2 DEMUX
1
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DEMUX

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User Image Dhrithi

2 to 1 DEMUX

2 to 1 DEMUX
1
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By using universal gate


project.name
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User Image Dhrithi

4 to 2 decoder

4 to 2 decoder
1
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Encoder and Decoder logic gates

project.name
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User Image Dhrithi

4 to 2 Priority encoder

4 to 2 Priority encoder
1
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Priority encoder

project.name
0 Stars     36 Views
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User Image Rakshitha

LEVEL 2: Priority encoder

LEVEL 2: Priority encoder
1
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A:2 Priority encoder

project.name
0 Stars     28 Views
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User Image Dhrithi

Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
1
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Experiment 5

level 1

project.name
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User Image Dhrithi

D to JK flip flop conversion

D to JK flip flop conversion
1
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Experiment 6

Level 2

project.name
0 Stars     25 Views
User:
User Image Rakshitha

level 2:exp 6 JK To D Flip-flop conversion

level 2:exp 6 JK To D Flip-flop conversion
1 6
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JK TO D FLIP-FLOP CONVERSION

project.name
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User Image Dhrithi

D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
1 2 3 4
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Experiment 6

Level 1

project.name
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User Image Phan Thanh Bảo

CEA

CEA
1
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project.name
0 Stars     49 Views
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User Image Miguel Arnold

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7
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his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent

project.name
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User Image ekaksh mishra

To study and verify logic gates

To study and verify logic gates
experiment 1
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experiment no 1

project.name
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User Image ekaksh mishra

To study and verify logic gates

To study and verify logic gates
experiment 1
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project.name
0 Stars     14 Views
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User Image Mufeez Ali

mufeez project 1

mufeez project 1
1
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project.name
0 Stars     35 Views
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User Image Suraj B

question 4

question 4
4. Design a combinational circuit with three inputs x y z and three outputs A B C. When the binary input is 0 1 2 or 3 the binary output is one greater than the input. When the binary input is 4 5 6 or 7 the binary output is one less than the input.
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project.name
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User Image Gustavo Ortiz

Mapas K (5 bits)

Mapas K (5 bits)
F(ABCDE)={18 29 5 31 10 21 14 3 7 26 16 1 9 23 28 12 6 0 20 17 30 11 25 4 19}
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project.name
0 Stars     18 Views
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User Image Bhavani Satish Kumar

Basic gates

Basic gates
1 2 at
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project.name
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User Image Raushan Yadav

Raushan Yadav

Raushan Yadav
1
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complete gate project

project.name
0 Stars     9 Views
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User Image Saishree N

Untitled1

Untitled1
1
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project.name
0 Stars     21 Views
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User Image Madhu sudhan

Untitled

Untitled
EXPERIMENT 1
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project.name
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User Image Chahat Singh

titled

titled
1
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project.name
0 Stars     14 Views
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User Image Jagdeesh Kumar Pal

assingment1

assingment1
1
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project.name
0 Stars     10 Views
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User Image VISHWANATH JOSHI

exp-3

exp-3
1
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project.name
0 Stars     15 Views
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User Image huang1234399

Untitled

Untitled
1
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first

project.name
0 Stars     19 Views
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User Image Prince Mapumah

lab4

lab4
1 2
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project.name
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User Image Prince Mapumah

lab4

lab4
2 1
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project.name
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User Image Prince Mapumah

lab4

lab4
1 2
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project.name
0 Stars     24 Views
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User Image Rahma Fitri Annisa

Untitled

Untitled
1 4 7
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project.name
0 Stars     25 Views
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User Image Toka

Untitled

Untitled
1 2
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project.name
0 Stars     14 Views
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User Image Aline Brincker

Digitale Logik

Digitale Logik
1
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project.name
0 Stars     9 Views
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User Image vansh

multiplexer

multiplexer
1
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project.name
0 Stars     15 Views
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User Image Nikola Gaborov

1

1
1
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8 segment

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0 Stars     19 Views
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User Image Pandu Ari Wijaya

ENCODER

ENCODER
1
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User Image Luis Leonardo

Ej 1

Ej 1
Ej 1
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project.name
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User Image Prof Narendra Kumar

1

1
1
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project.name
0 Stars     46 Views
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User Image Steve

Steve B. Badayos

Steve B. Badayos
t I n G S 1 2 h
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project.name
0 Stars     45 Views
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User Image Renz Labao

MATT DANIEL PEPINO

MATT DANIEL PEPINO
g H o S t Y 1 8
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project.name
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User Image Daniel Dressel

Nr.6

Nr.6
1
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project.name
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User Image Gabriel

Untitled

Untitled
1
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project.name
0 Stars     17 Views
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User Image divyashree

Untitled

Untitled
1
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project.name
0 Stars     17 Views
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User Image S.B. Veeranna

NOT Gate

NOT Gate
1
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0 Stars     10 Views
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User Image Vlad_PN

Мультиплексори та демультиплексори.

Мультиплексори та демультиплексори.
1
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project.name
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User Image Russ Gebrengus

Untitled

Untitled
1
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class work creating a circuit sympols 

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User Image Keerti Neeramanigar

Keerti N1

Keerti N1
1
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project.name
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User Image Gangapalli Pallavi

Untitled

Untitled
1
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project.name
0 Stars     9 Views
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User Image L GURU KIRAN

Untitled

Untitled
1
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project.name
0 Stars     12 Views
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User Image SHREYAS S RAMAN

EXPT 02

EXPT 02
1
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User Image Ruchi

S R Flip-Flop using NAND Gate

S R Flip-Flop using NAND Gate
1
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0 Stars     7 Views
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User Image Maryam Alfraidy

Untitled

Untitled
1
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project.name
0 Stars     8 Views
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User Image jahnavi

Untitled

Untitled
1
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project.name
0 Stars     9 Views
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User Image jahnavi

4*1 multiplexer

4*1 multiplexer
1
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project.name
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User Image jahnavi

8*1 mul;tiplexer

8*1 mul;tiplexer
1
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project.name
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User Image veeresh

Untitled

Untitled
1
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experiment 2

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User Image sterie mioara

Lab1 sterie mioara

Lab1 sterie mioara
lab 1
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project.name
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User Image Rafael Sang-Yum

Basic Gates

Basic Gates
Basic Gates Learning 1
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User Image Gnana PrasannaV

8*1

8*1
1
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project.name
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User Image Thanushree H J

EXPERIMENT:2

EXPERIMENT:2
1
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project.name
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User Image Thanushree H J

Untitled

Untitled
1
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project.name
1 Stars     26 Views
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User Image Thanushree H J

HALF ADDER AND HALF SUBTRACTOR

HALF ADDER AND HALF SUBTRACTOR
1
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User Image 小宇

Untitled

Untitled
1
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project.name
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User Image CHEA KIMHORN

k

k
1
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Untitled

Untitled
1
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O recapitulare la lab 4

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User Image Dulitha Weerasinghe

1

1
1
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project

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User Image Dulitha Weerasinghe

1

1
1
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project

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User Image Sebastián González Del Moral

Actividad2.A01786196

Actividad2.A01786196
proyect 1
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Actividad 2: A01786196

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3X8 decoders

3X8 decoders
1
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Untitled

Untitled
1
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User Image Axiel David Raul Yancachajlla Rinza

AXIEL C3 COMPARADOR

AXIEL C3 COMPARADOR
1
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Untitled

Untitled
1
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digital

digital
1
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Untitled1

Untitled1
1
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123

123
1
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User Image Mukhlis

pertama

pertama
1
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User Image Eng_Aakash

HALF SUB

HALF SUB
1
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User Image PETNIKORN SUVANKAW

1

1
1
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User Image Avinash Raj

DLD Q2

DLD Q2
Design of a sequential circuit for counting a sequence 0 1 2 4 5 and 6
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User Image Anurag

lvl 2

lvl 2
1
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User Image Nicolas Ignacio

1

1
1
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User Image jafet

tarea2pro2.1

tarea2pro2.1
tarea2 pro2 1
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User Image Chinmai A

PROJECT-1

PROJECT-1
1
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ECE2007_P

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User Image SUMIT DHAKA

EXP.1

EXP.1
1
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ALL GATES

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User Image anotony kenson

verification of logic gates 1(antony kenson)

verification of logic gates 1(antony kenson)
1
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User Image Avneesh kumar tripathi

gates

gates
1
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User Image anotony kenson

verification of boolean laws 1

verification of boolean laws 1
1
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User Image ASHWIN

HALF ADDER CIRCUIT

HALF ADDER CIRCUIT
1
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HALF ADDER CIRCUIT:

It is a basic building block of a full adder and other circuits.It consists of two important parts as outputs sum and carry.it is a method of binary addition which consits if X-or gate and AND gate.The combination of two outputs is called the half adder circuit.

Sum-It is the Least Significant Bit 

Carry-It is the Most Significant Bit

It need two K-maps




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Annulment Law

Annulment Law
1
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User Image Kalpana C Rathod

kalpana ECE LAB

kalpana ECE LAB
Logic gates 1
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User Image shrutika

exp 2

exp 2
EXPT 1
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project.name
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User Image Prasad Kalas

VERIFICATION OF LOGIC GATES

VERIFICATION OF LOGIC GATES
1
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User Image MINJAE KANG

1

1
1
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project.name
0 Stars     9 Views
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User Image himanshu gupta

3*8 decoder

3*8 decoder
1
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project.name
0 Stars     20 Views
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User Image BHASKARG

BHASKAR

BHASKAR
1
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project.name
0 Stars     20 Views
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User Image Jonás

jonas

jonas
1
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project.name
0 Stars     8 Views
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User Image Krishik.R

PROJECT 1

PROJECT 1
1
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project.name
0 Stars     8 Views
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User Image Devang samor

flip flop

flip flop
lab1 1
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0 Stars     10 Views
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User Image prajwal reddy

PRAJWAL REDDY

PRAJWAL REDDY
1
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project.name
0 Stars     13 Views
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User Image Thodoris Botsolos

chapter1

chapter1
1
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project.name
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Logic

Logic
1
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4bit full subtractor

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LDDCC

LDDCC
1
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project.name
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User Image Artem potridenniy2

ДЕШЕФРАТОР

ДЕШЕФРАТОР
ДЕШЕФРАТОР 1 2 3 4 битный
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Дешефрирует двоичные числа в десятичные от 1 до 4. Левая лампа 1. Правая лампа 4.

project.name
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User Image Daniel Sinaga

123

123
1
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project.name
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AND Gatter

AND Gatter
1
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project.name
1 Stars     9 Views
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User Image Nihal Sulagodu

1234567890

1234567890
1 2 3 4 5 6 7 8 9 0
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project.name
0 Stars     7 Views
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User Image SHAILESH RUSHIT

Rushit

Rushit
Practical 1
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project.name
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User Image Roshan yadav

Q2 lab1 using NAND gate

Q2 lab1 using NAND gate
1
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User Image Manoj vadhan T N

MANOJ

MANOJ
1 2 3
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operators

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User Image MUHAMMAD WALEED

DLD Lab Project

DLD Lab Project
6 7 3 5 0 9 4 2 1
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0 Stars     4 Views
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User Image hafza

HAFZA DLD

HAFZA DLD
DLD CIRCUIT 1
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