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Prueba

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practica1

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borrador1

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MULTIPLEXOR 4 X 1

MULTIPLEXOR 4 X 1
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Circuito secuencial

Circuito secuencial
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distancia h

distancia h
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ejercicio3.ALU

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csa1

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Store inf

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Инфа

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ымсвы
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ring counter

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dld
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circuit 1

circuit 1
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louis

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1

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Sprawdzian Eutk

Sprawdzian Eutk
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3*8

3*8
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Circuito caracol

Circuito caracol
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cicuito caracol lectura 1101

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De-Morgan’s Law using two variables.

De-Morgan’s Law using two variables.
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TP4 -1

TP4 -1
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AND

AND
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Ayça

Ayça
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User Image 1960627 NIKHIL GUPTA

Experiment 1

Experiment 1
1 2a 2b 3 4a 4b 5 6 7a 7b 8 9
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NIKHIL GUPTA 

1960627

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Experiment 1

Experiment 1
1
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My first experiment in DE lab.

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EX3

EX3
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not

not
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1 project

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1

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xor 1

xor 1
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[email protected]

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1 Circuit

1 Circuit
1 circuit
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XY'+(X+Y)'=A

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Entregable

Entregable
Entregable 1
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Primer entregable parcial

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janjuas project

janjuas project
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Lab1

Lab1
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CODE CONVERTOR

CODE CONVERTOR
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multiplexor

multiplexor
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test

test
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j

j
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CircuitVerse

CircuitVerse
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Untitled

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111

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NIRAJ DE

NIRAJ DE
DE 1
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lab 6

lab 6
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memoria

memoria
1
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memoria digitales 2

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User Image Miguel Ángel Medina Arellanes

Untitled

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Expt1

Expt1
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Activity 3

Activity 3
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LAB1

LAB1
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Logic Gates

Logic Gates
1
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14 september 2021 year


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Half and Full Adder

Half and Full Adder
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Untitled

Untitled
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ACTIVITY 4

ACTIVITY 4
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7 sagment displays

7 sagment displays
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lab 1

lab 1
lab 1
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naveen

naveen
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Nam

Nam
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lOGES

lOGES
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10

10
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AHMED HAMODA

AHMED HAMODA
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13-1

13-1
13 1
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13,1

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Informatik 1

Informatik 1
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project.name
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DC Lab

DC Lab
1 2 3 4
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User Image 20bcs011 Hitesh vashisth

lab assignment

lab assignment
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KSA

KSA
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DEMORGANS LAW

DEMORGANS LAW
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project.name
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trab final

trab final
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21UCS051_Exp9

21UCS051_Exp9
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Half Adder

Half Adder
Half adder 1
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Half adder

Half adder
Half adder 1
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Untitled

Untitled
#3 1
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Didier Circuito

Didier Circuito
Circuito 1
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Tarea lab Sis. digitales

Tarea lab Sis. digitales
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20524068_Muhamad Taruna_1

20524068_Muhamad Taruna_1
SISDIG 1
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project.name
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User Image Muhamad Taruna Pramudhita

20524068_Muhamad Taruna_2

20524068_Muhamad Taruna_2
SISDIG 1
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project.name
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SKILL BASED MINI PROJECT

SKILL BASED MINI PROJECT
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SKILL BASED NANDINI

SKILL BASED NANDINI
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project.name
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User Image Abdul Wahid

decoder

decoder
1
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project.name
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shaik munawar,20211csg0072

shaik munawar,20211csg0072
experiment 1
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project.name
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User Image Pragya Mittal

full adder

full adder
1
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User Image Jeisson fabian Torres contreras

punto 1 taller 2

punto 1 taller 2
1
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project.name
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User Image Andre Magtibay

2

2
1
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project.name
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User Image Michael Powell

Michael Powell - CircuitVerse_CSX_1

Michael Powell - CircuitVerse_CSX_1
CSX 1
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This circuit determines if two triangles are congruent given a set of six inputs relating the triangles' side lengths and angle measures.

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User Image muneeraibraheem

Untitled1

Untitled1
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User Image 吳尚哲

Untitled

Untitled
1
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project.name
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User Image 727821TUEC122 MONIKA SRI B.

RS flipflop

RS flipflop
1
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rs flipflop

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User Image 727821TUEC124 NANDITHA V.

RS FLIPFLOP

RS FLIPFLOP
1
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User Image Mustafa Can Buyuksari

Untitled1

Untitled1
1
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project.name
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seven segment

seven segment
logic 1
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User Image Peyton McCarrick

Project 1

Project 1
1
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project.name
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piso

piso
1
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project.name
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User Image Navya Arveti

experiment 1

experiment 1
1
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project.name
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User Image Dhrithi

Half adder using XOR and NAND

Half adder using XOR and NAND
1
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Experiment 2

Level 1


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Full adder using XOR and NAND

Full adder using XOR and NAND
1
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Experiment 2

Level 1


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half subtractor using XOR and NANAD Gates

half subtractor using XOR and NANAD Gates
1
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half subtractor

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User Image Dhrithi

Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
1 2
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Experiment 1

Level 2


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User Image PAVANI AMMU

20221CBD0014

20221CBD0014
1
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project.name
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User Image Dhrithi

3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
1
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Level 2


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3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
1
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Level 2

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Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
1
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Logic circuit of 2-to-1 Multiplexer

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User Image PAVANI AMMU

20221CBD0014

20221CBD0014
1
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project.name
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User Image Dhrithi

2 to 1 multiplexer

2 to 1 multiplexer
1
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Realization of 2 to 1 MUX using basic and XOR gate

project.name
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User Image Dhrithi

1 to 2 DEMUX

1 to 2 DEMUX
1
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DEMUX

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2 to 1 DEMUX

2 to 1 DEMUX
1
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By using universal gate


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User Image Dhrithi

4 to 2 decoder

4 to 2 decoder
1
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Encoder and Decoder logic gates

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User Image Dhrithi

4 to 2 Priority encoder

4 to 2 Priority encoder
1
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Priority encoder

project.name
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User Image Rakshitha

LEVEL 2: Priority encoder

LEVEL 2: Priority encoder
1
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A:2 Priority encoder

project.name
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User Image Dhrithi

Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
1
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Experiment 5

level 1

project.name
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User Image Dhrithi

D to JK flip flop conversion

D to JK flip flop conversion
1
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Experiment 6

Level 2

project.name
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User Image Rakshitha

level 2:exp 6 JK To D Flip-flop conversion

level 2:exp 6 JK To D Flip-flop conversion
1 6
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JK TO D FLIP-FLOP CONVERSION

project.name
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User Image Dhrithi

D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
1 2 3 4
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Experiment 6

Level 1

project.name
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User Image Phan Thanh Bảo

CEA

CEA
1
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project.name
0 Stars     5 Views
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User Image Miguel Arnold

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7
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his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent

project.name
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User Image ekaksh mishra

To study and verify logic gates

To study and verify logic gates
experiment 1
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experiment no 1

project.name
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User Image ekaksh mishra

To study and verify logic gates

To study and verify logic gates
experiment 1
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project.name
0 Stars     1 Views
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User Image Mufeez Ali

mufeez project 1

mufeez project 1
1
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project.name
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User Image Suraj B

question 4

question 4
4. Design a combinational circuit with three inputs x y z and three outputs A B C. When the binary input is 0 1 2 or 3 the binary output is one greater than the input. When the binary input is 4 5 6 or 7 the binary output is one less than the input.
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project.name
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User Image Gustavo Ortiz

Mapas K (5 bits)

Mapas K (5 bits)
F(ABCDE)={18 29 5 31 10 21 14 3 7 26 16 1 9 23 28 12 6 0 20 17 30 11 25 4 19}
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project.name
0 Stars     1 Views
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User Image Bhavani Satish Kumar

Basic gates

Basic gates
1 2 at
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project.name
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User Image Raushan Yadav

Raushan Yadav

Raushan Yadav
1
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complete gate project

project.name
0 Stars     1 Views
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User Image Saishree N

Untitled1

Untitled1
1
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project.name
0 Stars     1 Views
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User Image Madhu sudhan

Untitled

Untitled
EXPERIMENT 1
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project.name
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User Image Chahat Singh

titled

titled
1
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project.name
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User Image Jagdeesh Kumar Pal

assingment1

assingment1
1
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project.name
0 Stars     1 Views
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User Image VISHWANATH JOSHI

exp-3

exp-3
1
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project.name
0 Stars     1 Views
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User Image huang1234399

Untitled

Untitled
1
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first

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User Image Prince Mapumah

lab4

lab4
1 2
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project.name
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User Image Prince Mapumah

lab4

lab4
2 1
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project.name
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User Image Prince Mapumah

lab4

lab4
1 2
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project.name
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User Image Rahma Fitri Annisa

Untitled

Untitled
1 4 7
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project.name
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User Image Toka

Untitled

Untitled
1 2
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project.name
0 Stars     1 Views
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User Image Aline Brincker

Digitale Logik

Digitale Logik
1
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project.name
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User Image vansh

multiplexer

multiplexer
1
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project.name
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User Image Nikola Gaborov

1

1
1
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8 segment

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User Image Pandu Ari Wijaya

Untitled

Untitled
1
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project.name
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User Image Luis Leonardo

Ej 1

Ej 1
Ej 1
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project.name
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User Image Prof Narendra Kumar

1

1
1
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project.name
0 Stars     1 Views
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User Image Steve

Steve B. Badayos

Steve B. Badayos
t I n G S 1 2 h
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User Image Renz Labao

MATT DANIEL PEPINO

MATT DANIEL PEPINO
g H o S t Y 1 8
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