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Tags: Computer Architecture

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Sumadores Binarios. Half - Adder, Full - Adder y un 4-bit Adder


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File Register for RISC-V

File Register for RISC-V

This module implemets the Register File of a basic version of RISC-V processor.


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Instruction Decoder

Instruction Decoder

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32-Bit MIPS Processor

32-Bit MIPS Processor

This project entails the building of a Single-Cycle MIPS ISA Processor.
I probably won't be able to build the entire processor because of the amount of instructions, and time it'll take, but it'll be a start.