Sumadores Binarios. Half - Adder, Full - Adder y un 4-bit Adder
This module implemets the Register File of a basic version of RISC-V processor.
This project entails the building of a Single-Cycle MIPS ISA Processor.
I probably won't be able to build the entire processor because of the amount of instructions, and time it'll take, but it'll be a start.