Searched Projects

Tags: trit

project.name
1 Stars     182 Views
User:

(PLEASE SEE THE NEWER MORE UP TO DATE VERSION OF THIS PROJECT ON MY PROFILE)

t729 is a 6/12-trit balanced ternary processor.

It is built with normal binary logic gates using binary encoded ternary (10, 00, 01) to create the ternary logic gates. While this probably increases complexity, I've not found a logic simulator that does ternary. I tried circuit simulators but working with negative and positive voltages with transistors is kind of a pain and very slow to design. Sure binary encoded ternary is more wire complex but it does only require one voltage and should technically use less power and run faster. Also binary logic gates are super cheap. Using binary logic gates also means the design should work on FPGAs and could in theory get manufactured as a microprocessor.

I've gone with 6-trit = 1 Tryte for my system. 12-trit / 2 Tryte is a "word".

Data and instruction width is 6-trit (729)
Address width is 12-trit (531,441)

The t729 is a hobby project I've been extremely slowly working on for a few years. It's purely a project for fun. Completely self taught so probably a lot of doing things the wrong way.

Currently I'm mostly hung up on instruction set. It's hard choosing which instructions to have and how to implement them.

Huge thanks to http://homepage.divms.uiowa.edu/~jones/ternary/ for the ternary logic knowledge.

If you would like to add something to the project or point something out please comment or e-mail (gmail*dyne.unlimited)


project.name
2 Stars     225 Views
User:

I have created a Wiki for my project: https://t729.mrdyne.net/

t729 is a 6/12-trit balanced ternary processor.

It is built with normal binary logic gates using binary encoded ternary (10, 00, 01) to create the ternary logic gates. While this probably increases complexity, I've not found a logic simulator that does ternary.

I've gone with 6-trit = 1 Tryte for my system. 12-trit / 2 Tryte is a "word".

Data and instruction width is 6-trit (729)
Address width is 12-trit (531,441)

The t729 is a hobby project I've been extremely slowly working on for a few years. It's purely a project for fun. Completely self taught so probably a lot of doing things the wrong way.

Currently I'm mostly hung up on instruction set. It's hard choosing which instructions to have and how to implement them.

Huge thanks to this website's Author http://homepage.divms.uiowa.edu/~jones/ternary/ for the starting ternary logic knowledge.

If you would like to discuss my project or other ternary related topics you can contact me at

mrdyne $ mrdyne * net.


project.name
2 Stars     15 Views
User:

This project showcases a Trit RAM designed for ternary logic simulation within CircuitVerse. The RAM features 729 addresses, arranged in 27 columns and 27 rows, all controlled by 3 trits for both row and column selection. This design represents an efficient approach to ternary memory, pushing the limits of CircuitVerse's simulation capabilities.

While the original goal was to create a RAM with 19,683 addresses, the complexity caused significant performance issues in the simulator, prompting a scaled-down version that operates smoothly on standard hardware.

Key Details:

  • Memory Size: 729 addresses (3^6).
  • Addressing Scheme: 3 trits each for row and column selection, enabling precise access to memory cells.
  • Splitters as Wires: Due to CircuitVerse’s limitations, splitters are treated as single wires to maintain simulation efficiency.
  • Performance Optimization: Designed to balance functionality and simulator stability, making it ideal for testing ternary logic concepts like ALUs and memory structures.

This project is an essential building block for advancing ternary computing within a binary-focused simulation tool, paving the way for innovative designs.