Searched Projects

4 Bit Asynchronous Counter using JK Flip-FLop

Two bit Asynchronous up counter that counts from 00 to 11 and back.

JK Flip Flop using SR Flip Flop (implemented with NOR gates)

Reference: The Essentials of Computer Organization and Architecture, 5th Edition. Linda Null and Julia Lobur. Chapter 3, pages 178 - 179.

Sequential circuit used in Exercise 62 from Null & Lobur, Computer Organization and Architecture, 5th Ed.

JK Flip Flop

A collection of different JK Flip Flop Circuits. If you're finding this from the CDA Computer Org review the Basic JK Flip Flop is the circuit we learned about in class.

(See this Stack Exchange post for more info https://electronics.stackexchange.com/questions/491352/jk-latch-possible-ben-eater-error/491439#491439)

A school project to simulate the functionality of a 60 s counter for a jk fliplop circuit

This is from a small project that was done for school, the purpose for saving this online is so that the teacher can interact with it and grade it for himself.

Thesequential circuit employed in this project is a synchronous counter using JK flip flop, which counts through the series 7,2,3,0,4,2..

Firstly the state diagram of counter was employed: 000->100->111->010->011->000.

Since sequence involves 3 bit number, number of flip flops employed= 3

Based on state diagram, table representing present state and next state was developed [(Q₂,Q₁,Q₀) and (Q2⁺,Q1+,Q0+)].  -- table(1)

Characteristic Table for JK Flip Flop: 

From Characteristic table, expression for  input J and K were developed using K map.(3 different expression for J and K)

J₂=Q₁'          K₂=Q₁

J₁ = Q₂          K₁=Q₂' Q₀

J₀=Q₁+Q₂    K₀=Q₀ 

To implement the values of J and K necessary gates were employed, and common clock was given to all 3 flip flops