project.name

Rakshana S

Member since: 595 days

Educational Institution: Not Entered

Country: Not Entered

DPSD

DPSD
Public
DPSD

DESIGN OF ADDER AND SUBTRACTOR

DESIGN OF ADDER AND SUBTRACTOR
Public
DESIGN OF ADDER AND SUBTRACTOR

DESIGN AND IMPLEMENTATION OF MULTIPLEXER

DESIGN AND IMPLEMENTATION OF MULTIPLEXER
Public
DESIGN AND IMPLEMENTATION OF MULTIPLEXER

T FLIP FLOP

T FLIP FLOP
Public
T FLIP FLOP

STUDY OF LOGIC GATES

STUDY OF LOGIC GATES
Public
STUDY OF LOGIC GATES

FULL ADDER

FULL ADDER
Public
FULL ADDER

DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

DESIGN AND IMPLEMENTATION OF CODE CONVERTORS
Public
DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

JK FLIP FLOP

JK FLIP FLOP
Public
JK FLIP FLOP

BCD PART 2

BCD PART 2
Public
BCD PART 2

D FLIP FLOP

D FLIP FLOP
Public
D FLIP FLOP

EX NO1

EX NO1
Public
EX NO1

IMPLEMENTATION OF SHIT REGISTER

IMPLEMENTATION OF SHIT REGISTER
Public
IMPLEMENTATION OF SHIT REGISTER

fghhg

fghhg
Public
fghhg

HALF ADDER

HALF ADDER
Public
HALF ADDER

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
Public
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES
Public
VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
Public
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER

DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER
Public
DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER
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