Rakshana S
Member since: 595 days
Educational Institution: Not Entered
Country: Not Entered
DPSD
DPSD
Public
DESIGN OF ADDER AND SUBTRACTOR
DESIGN OF ADDER AND SUBTRACTOR
Public
DESIGN AND IMPLEMENTATION OF MULTIPLEXER
DESIGN AND IMPLEMENTATION OF MULTIPLEXER
Public
T FLIP FLOP
T FLIP FLOP
Public
STUDY OF LOGIC GATES
STUDY OF LOGIC GATES
Public
FULL ADDER
FULL ADDER
Public
DESIGN AND IMPLEMENTATION OF CODE CONVERTORS
DESIGN AND IMPLEMENTATION OF CODE CONVERTORS
Public
JK FLIP FLOP
JK FLIP FLOP
Public
BCD PART 2
BCD PART 2
Public
D FLIP FLOP
D FLIP FLOP
Public
EX NO1
EX NO1
Public
IMPLEMENTATION OF SHIT REGISTER
IMPLEMENTATION OF SHIT REGISTER
Public
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Public
HALF ADDER
HALF ADDER
Public
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
Public
VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES
VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES
Public
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
Public
DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER
DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER
Public
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