Flip Flop Using NAND GATE
SR, JK, D, T Flip Flop
Description:
1) Implement, truth table and generate waveform
2) D, T, SR, JK- latch using NAND and NOR gates
3) D, T, SR, JK - FF using NAND and NOR gates
4) D-FF using SR-FF
5) Master-slave JK-FF using NAND Gate
Project with all the Latches and Flipflops constructed from scratch with Logic gates. With comments/explanations.
Features:
Latches: Set-Reset, Set-Reset-Toggle, Delay
Flipflops: Set-Reset, Delay, Toggle, Jump and Kill