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project.name
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Untitled

Untitled
2

project.name
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HARSHIT

HARSHIT
2

project.name
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pract2

pract2
2

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2'complement

2'complement
2

project.name
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AYÇA METİN

AYÇA METİN
2

project.name
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Experiment 1

Experiment 1
2

The second lab experiment using simulator.


project.name
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Or

Or
2

project.name
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2 практика

2 практика
2

project.name
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full adder using 2 half adder

full adder using 2 half adder

project.name
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3-8 line decoder

3-8 line decoder
2

project.name
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Experoment no 2

Experoment no 2

Test functionality of Universal gates.


project.name
1 Stars     76 Views

Practicle 2

Practicle 2

AIM


project.name
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verification of de morgan law

verification of de morgan law
L A B 2

project.name
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maan g cade

maan g cade
2

w2w


project.name
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Activity 3

Activity 3
1 2 3 4 5

project.name
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LAB2

LAB2
2

2


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Comparadores

Comparadores

project.name
0 Stars     64 Views

Sumadores

Sumadores

project.name
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UL_ARQ_3

UL_ARQ_3

project.name
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Assignment

Assignment
2

project.name
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Activity 4

Activity 4
2

project.name
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0 to 2 counter

0 to 2 counter

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Untitled

Untitled
2

project.name
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13-2

13-2
13 2

13,2


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DC Lab

DC Lab
1 2 3 4

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LAB ASSIGNMENT 20BCS011

LAB ASSIGNMENT 20BCS011
2

project.name
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trab circui

trab circui
2

project.name
0 Stars     75 Views
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21UCS051_Exp9

21UCS051_Exp9
2

project.name
0 Stars     53 Views

Clase 3 de Mayo

Clase 3 de Mayo

project.name
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Michael Powell - CircuitVerse_CSX_2

Michael Powell - CircuitVerse_CSX_2
CSX 2

This circuit determines what theorems in calculus are guaranteed for a function given a set of five inputs.


project.name
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2*4 decoder

2*4 decoder
2

project.name
0 Stars     9 Views

manmeet

manmeet
2

digital gates



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1 Stars     12 Views
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20221CBD0014

20221CBD0014
2

project.name
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20221CBD0014

20221CBD0014
2

project.name
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Half subtractor using XOR and NAND

Half subtractor using XOR and NAND
2

Experiment 2

Level 1



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Full Subtractor using XOR and NAND

Full Subtractor using XOR and NAND
2

Experiment 2

Level 1



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full adder

full adder
2

full adder


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Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
1 2

Experiment 1

Level 2



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3 bit Full subtractor using NAND gate

3 bit Full subtractor using NAND gate
2

Level 2


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3 bit half subtractor using NAND gate

3 bit half subtractor using NAND gate
2

Level 2


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4 to 1 MUX

4 to 1 MUX
2

Realization of 4 to 1 MUX using basic gates and XOR gate


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1 to 4 DE-Multiplexer

1 to 4 DE-Multiplexer
2

De-Multiplexer


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4 to 1 DEMUX

4 to 1 DEMUX
2

By using universal gates


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2 to 4 decoder

2 to 4 decoder
2

Encoder and decoder logic gates


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4 to 2 Priority encoder

4 to 2 Priority encoder
2

Priority encoder


project.name
0 Stars     13 Views
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Design of Logic Diagram using NAND gate-exp 5

Design of Logic Diagram using NAND gate-exp 5
2

Experiment 5


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exp 5: design of logic diagram using NAND gates

exp 5: design of logic diagram using NAND gates
5 2

exp 5-using NAND Gates


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JK to D flip flop conversion

JK to D flip flop conversion
2

Experiment 6 

Level 2


project.name
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D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
1 2 3 4

Experiment 6

Level 1


project.name
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EXP 6: D,T,SR,JK Flip-flops

EXP 6: D,T,SR,JK Flip-flops
4 2

FLIPS-FLOPS


project.name
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Assignment4

Assignment4
Q.1 2 3 4 5

project.name
0 Stars     40 Views

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7

his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent


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project.name
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Basic gates

Basic gates
1 2 at

project.name
0 Stars     10 Views

Untitled

Untitled
2

project 2


project.name
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EXP_1

EXP_1
L_1 2

project.name
0 Stars     14 Views
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punto dos del parcial

punto dos del parcial
P 2

project.name
0 Stars     15 Views

lab4

lab4
1 2

project.name
0 Stars     16 Views

lab4

lab4
2 1

project.name
0 Stars     17 Views

lab4

lab4
1 2

project.name
0 Stars     12 Views
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Untitled

Untitled
1 2

project.name
0 Stars     32 Views
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Steve B. Badayos

Steve B. Badayos
t I n G S 1 2 h

project.name
0 Stars     37 Views

CABANERO AND VELARDE

CABANERO AND VELARDE
L o u S A 2 3

project.name
0 Stars     9 Views

EXP8

EXP8
2

project.name
0 Stars     15 Views
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circuis

circuis
lab 2

project.name
0 Stars     7 Views
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JK flip flop

JK flip flop
2

project.name
0 Stars     12 Views

harshita ds

harshita ds

project.name
0 Stars     15 Views
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experiment3

experiment3

project.name
0 Stars     7 Views

Untitled

Untitled
2

project.name
0 Stars     11 Views

tema2steriemioara

tema2steriemioara
lab 2

project.name
0 Stars     9 Views

EXP-2

EXP-2
2

project.name
1 Stars     10 Views

FULL ADDER AND FULL SUBTRACTOR

FULL ADDER AND FULL SUBTRACTOR
2

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Multiplexoare

Multiplexoare
2

project.name
0 Stars     11 Views
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EX 7

EX 7

project.name
0 Stars     10 Views

safa imtiaz

safa imtiaz

project.name
0 Stars     6 Views
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HALF ADDER

HALF ADDER
2

project.name
0 Stars     6 Views
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GRAY CODE TO BINARY CODE

GRAY CODE TO BINARY CODE
2 3

project.name
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project.name
0 Stars     7 Views

verification of logic gates 2

verification of logic gates 2
2

project.name
0 Stars     5 Views
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Untitled

Untitled
2

project.name
0 Stars     5 Views

verifiction of boolean laws 2

verifiction of boolean laws 2
2

project.name
0 Stars     5 Views

Identity Law

Identity Law
2

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PROJECT.2

PROJECT.2
2

project.name
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PROJECT2

PROJECT2
2

project.name
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PROJECT2

PROJECT2
2

project.name
0 Stars     5 Views
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BHASKAR G

BHASKAR G
2

project.name
1 Stars     8 Views
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william patiño

william patiño

project.name
0 Stars     7 Views
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Untitled

Untitled

project.name
0 Stars     3 Views

8/1 multiplexer

8/1 multiplexer
2

project.name
0 Stars     5 Views

ДЕШЕФРАТОР

ДЕШЕФРАТОР

Дешефрирует двоичные числа в десятичные от 1 до 4. Левая лампа 1. Правая лампа 4.