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project.name
0 Stars     117 Views
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User Image Iris Rocio Curo Quispe

Untitled

Untitled
2
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project.name
0 Stars     116 Views
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User Image Harshit Agarwal

HARSHIT

HARSHIT
2
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project.name
0 Stars     92 Views
User:
User Image дмитрий красножен

pract2

pract2
2
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project.name
0 Stars     115 Views
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User Image Phearun Ol

2'complement

2'complement
2
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project.name
0 Stars     51 Views
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User Image Ayça

AYÇA METİN

AYÇA METİN
2
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project.name
0 Stars     55 Views
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User Image Sharun E Rajeev

Experiment 1

Experiment 1
2
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The second lab experiment using simulator.

project.name
0 Stars     46 Views
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User Image LUCAS HENRIQUE MANHANI

Or

Or
2
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project.name
0 Stars     44 Views
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User Image Shikuro

2 практика

2 практика
2
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project.name
0 Stars     108 Views
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User Image SUNDHARA DHARSHINI R

full adder using 2 half adder

full adder using 2 half adder
full adder using 2 half
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project.name
0 Stars     48 Views
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User Image Rishika

3-8 line decoder

3-8 line decoder
2
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project.name
0 Stars     52 Views
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User Image Jayashri

Experoment no 2

Experoment no 2
expt 2
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Test functionality of Universal gates.

project.name
1 Stars     72 Views
User:
User Image MAYANK AGRAWAL

Practicle 2

Practicle 2
COA practical file 2
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AIM

project.name
0 Stars     61 Views
User:
User Image Mandar Uday Patil

verification of de morgan law

verification of de morgan law
L A B 2
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project.name
0 Stars     41 Views
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User Image Abdirahman gedi

maan g cade

maan g cade
2
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w2w

project.name
0 Stars     81 Views
User:
User Image Adrian Tuazon

Activity 3

Activity 3
1 2 3 4 5
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project.name
0 Stars     75 Views
User:
User Image Ji Kwang Kim

LAB2

LAB2
2
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2

project.name
0 Stars     56 Views
User:
User Image George Romero

Comparadores

Comparadores
comprador 2 bits
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project.name
0 Stars     62 Views
User:
User Image George Romero

Sumadores

Sumadores
sumador completo 2 bits
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project.name
0 Stars     64 Views
User:
User Image George Romero

UL_ARQ_3

UL_ARQ_3
sumador completo 2 bits
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project.name
0 Stars     25 Views
User:
User Image Mukhammadamin

Assignment

Assignment
2
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project.name
0 Stars     43 Views
User:
User Image Christopher Fernand0

Activity 4

Activity 4
2
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project.name
0 Stars     109 Views
User:
User Image Raul S.S

0 to 2 counter

0 to 2 counter
0 to 2 counter 0 to 2 counter
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project.name
0 Stars     25 Views
User:
User Image MOHAMAD HABASH

Untitled

Untitled
2
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project.name
0 Stars     69 Views
User:
User Image Keenan

13-2

13-2
13 2
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13,2

project.name
0 Stars     86 Views
User:
User Image Tarun Bansal

DC Lab

DC Lab
1 2 3 4
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project.name
0 Stars     28 Views
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User Image 20bcs011 Hitesh vashisth

LAB ASSIGNMENT 20BCS011

LAB ASSIGNMENT 20BCS011
2
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project.name
0 Stars     21 Views
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User Image Piero

trab circui

trab circui
2
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project.name
0 Stars     73 Views
User:
User Image Chirag

21UCS051_Exp9

21UCS051_Exp9
2
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project.name
0 Stars     53 Views
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User Image DAVID ESTEBAN BAUTISTA ALEMAN

Clase 3 de Mayo

Clase 3 de Mayo
Sumadores 1 2 4 bit
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project.name
0 Stars     15 Views
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User Image Michael Powell

Michael Powell - CircuitVerse_CSX_2

Michael Powell - CircuitVerse_CSX_2
CSX 2
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This circuit determines what theorems in calculus are guaranteed for a function given a set of five inputs.

project.name
0 Stars     9 Views
User:
User Image Harsh Gupta

2*4 decoder

2*4 decoder
2
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project.name
0 Stars     9 Views
User:
User Image Manmeet Rajput

manmeet

manmeet
2
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digital gates


project.name
1 Stars     11 Views
User:
User Image PAVANI AMMU

20221CBD0014

20221CBD0014
2
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project.name
0 Stars     11 Views
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User Image PAVANI AMMU

20221CBD0014

20221CBD0014
2
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project.name
0 Stars     16 Views
User:
User Image Dhrithi

Half subtractor using XOR and NAND

Half subtractor using XOR and NAND
2
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Experiment 2

Level 1


project.name
0 Stars     18 Views
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User Image Dhrithi

Full Subtractor using XOR and NAND

Full Subtractor using XOR and NAND
2
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Experiment 2

Level 1


project.name
0 Stars     15 Views
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User Image Rakshitha

full adder

full adder
2
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full adder

project.name
0 Stars     17 Views
User:
User Image Dhrithi

Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
1 2
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Experiment 1

Level 2


project.name
0 Stars     17 Views
User:
User Image Dhrithi

3 bit Full subtractor using NAND gate

3 bit Full subtractor using NAND gate
2
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Level 2

project.name
0 Stars     12 Views
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User Image Dhrithi

3 bit half subtractor using NAND gate

3 bit half subtractor using NAND gate
2
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Level 2

project.name
0 Stars     16 Views
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User Image Dhrithi

4 to 1 MUX

4 to 1 MUX
2
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Realization of 4 to 1 MUX using basic gates and XOR gate

project.name
0 Stars     14 Views
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User Image Dhrithi

1 to 4 DE-Multiplexer

1 to 4 DE-Multiplexer
2
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De-Multiplexer

project.name
0 Stars     16 Views
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User Image Dhrithi

4 to 1 DEMUX

4 to 1 DEMUX
2
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By using universal gates

project.name
0 Stars     15 Views
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User Image Dhrithi

2 to 4 decoder

2 to 4 decoder
2
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Encoder and decoder logic gates

project.name
0 Stars     14 Views
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User Image Dhrithi

4 to 2 Priority encoder

4 to 2 Priority encoder
2
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Priority encoder

project.name
0 Stars     12 Views
User:
User Image Dhrithi

Design of Logic Diagram using NAND gate-exp 5

Design of Logic Diagram using NAND gate-exp 5
2
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Experiment 5

project.name
0 Stars     17 Views
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User Image Rakshitha

exp 5: design of logic diagram using NAND gates

exp 5: design of logic diagram using NAND gates
5 2
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exp 5-using NAND Gates

project.name
0 Stars     14 Views
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User Image Dhrithi

JK to D flip flop conversion

JK to D flip flop conversion
2
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Experiment 6 

Level 2

project.name
0 Stars     19 Views
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User Image Dhrithi

D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
1 2 3 4
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Experiment 6

Level 1

project.name
0 Stars     25 Views
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User Image Rakshitha

EXP 6: D,T,SR,JK Flip-flops

EXP 6: D,T,SR,JK Flip-flops
4 2
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FLIPS-FLOPS

project.name
0 Stars     24 Views
User:
User Image Dipanshi Maurya 22220CMP007

Assignment4

Assignment4
Q.1 2 3 4 5
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project.name
0 Stars     36 Views
User:
User Image Miguel Arnold

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7
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his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent

project.name
0 Stars     26 Views
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User Image Suraj B

question 4

question 4
4. Design a combinational circuit with three inputs x y z and three outputs A B C. When the binary input is 0 1 2 or 3 the binary output is one greater than the input. When the binary input is 4 5 6 or 7 the binary output is one less than the input.
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project.name
0 Stars     12 Views
User:
User Image Bhavani Satish Kumar

Basic gates

Basic gates
1 2 at
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project.name
0 Stars     10 Views
User:
User Image Raushan Yadav

Untitled

Untitled
2
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project 2

project.name
0 Stars     9 Views
User:
User Image VAMSI POLISETTY

EXP_1

EXP_1
L_1 2
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project.name
0 Stars     14 Views
User:
User Image geimar

punto dos del parcial

punto dos del parcial
P 2
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project.name
0 Stars     15 Views
User:
User Image Prince Mapumah

lab4

lab4
1 2
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project.name
0 Stars     16 Views
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User Image Prince Mapumah

lab4

lab4
2 1
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project.name
0 Stars     16 Views
User:
User Image Prince Mapumah

lab4

lab4
1 2
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project.name
0 Stars     12 Views
User:
User Image Toka

Untitled

Untitled
1 2
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project.name
0 Stars     32 Views
User:
User Image Steve

Steve B. Badayos

Steve B. Badayos
t I n G S 1 2 h
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project.name
0 Stars     37 Views
User:
User Image Joanna marie Cabañero

CABANERO AND VELARDE

CABANERO AND VELARDE
L o u S A 2 3
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project.name
0 Stars     8 Views
User:
User Image Ayberk Kemal Tural

EXP8

EXP8
2
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project.name
0 Stars     15 Views
User:
User Image Samridhi

circuis

circuis
lab 2
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project.name
0 Stars     7 Views
User:
User Image Ruchi

JK flip flop

JK flip flop
2
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project.name
0 Stars     11 Views
User:
User Image harshita salunke

harshita ds

harshita ds
boolean laws 1 2 3.
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project.name
0 Stars     14 Views
User:
User Image ASWATHI

experiment3

experiment3
level 1 2
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project.name
0 Stars     7 Views
User:
User Image Basavaraj Biradar

Untitled

Untitled
2
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project.name
0 Stars     11 Views
User:
User Image sterie mioara

tema2steriemioara

tema2steriemioara
lab 2
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project.name
0 Stars     9 Views
User:
User Image Thanushree H J

EXP-2

EXP-2
2
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project.name
1 Stars     8 Views
User:
User Image Thanushree H J

FULL ADDER AND FULL SUBTRACTOR

FULL ADDER AND FULL SUBTRACTOR
2
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project.name
0 Stars     6 Views
User:
User Image Pupaza

Multiplexoare

Multiplexoare
2
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project.name
0 Stars     10 Views
User:
User Image lubna raina

EX 7

EX 7
LEVEL 1 2
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project.name
0 Stars     8 Views
User:
User Image Safa Imtiaz

safa imtiaz

safa imtiaz
2 3 4 or gates with led
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project.name
0 Stars     6 Views
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User Image Eng_Aakash

HALF ADDER

HALF ADDER
2
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project.name
0 Stars     5 Views
User:
User Image Srikanth svs

GRAY CODE TO BINARY CODE

GRAY CODE TO BINARY CODE
2 3
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project.name
0 Stars     5 Views
User:
User Image Avinash Raj

DLD Q2

DLD Q2
Design of a sequential circuit for counting a sequence 0 1 2 4 5 and 6
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project.name
0 Stars     6 Views
User:
User Image anotony kenson

verification of logic gates 2

verification of logic gates 2
2
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project.name
0 Stars     5 Views
User:
User Image Chinmai A

Untitled

Untitled
2
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project.name
0 Stars     5 Views
User:
User Image anotony kenson

verifiction of boolean laws 2

verifiction of boolean laws 2
2
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project.name
0 Stars     5 Views
User:
User Image Mohammed Azeemulla Khan

Identity Law

Identity Law
2
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project.name
0 Stars     6 Views
User:
User Image Chinmai A

PROJECT.2

PROJECT.2
2
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project.name
0 Stars     5 Views
User:
User Image Chinmai A

PROJECT2

PROJECT2
2
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project.name
0 Stars     5 Views
User:
User Image Chinmai A

PROJECT2

PROJECT2
2
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project.name
0 Stars     5 Views
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User Image BHASKARG

BHASKAR G

BHASKAR G
2
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project.name
1 Stars     7 Views
User:
User Image william

william patiño

william patiño
parcial 2
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project.name
0 Stars     6 Views
User:
User Image william

Untitled

Untitled
parcial 2
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project.name
0 Stars     3 Views
User:
User Image Bhoomi kumari Mehta

8/1 multiplexer

8/1 multiplexer
2
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