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project.name
0 Stars     117 Views
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User Image Iris Rocio Curo Quispe

multiplexador 4x1

multiplexador 4x1
5
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project.name
0 Stars     106 Views
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User Image Harshit Agarwal

HARSHIT

HARSHIT
5
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project.name
0 Stars     113 Views
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User Image Iris Rocio Curo Quispe

Hamming

Hamming
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project.name
0 Stars     75 Views
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User Image дмитрий красножен

Alu

Alu
5
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project.name
0 Stars     65 Views
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User Image samarjit sen

exp 5

exp 5
5
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project.name
0 Stars     80 Views
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User Image 1960627 NIKHIL GUPTA

Experiment 1

Experiment 1
1 2a 2b 3 4a 4b 5 6 7a 7b 8 9
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NIKHIL GUPTA 

1960627

project.name
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User Image shivam uniyal

EXPERIMENT 4

EXPERIMENT 4
5
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project.name
1 Stars     103 Views
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User Image D_2061008_M.Maria Anish

experement 2 2,3,4,5, question 2061008

experement 2 2,3,4,5, question 2061008
question 2 3 4 5
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 question no ; 2,3,4,5

project.name
0 Stars     43 Views
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User Image Rishika

T FLIPFLOP

T FLIPFLOP
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project.name
0 Stars     36 Views
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User Image Igor Hornburg

Untitled

Untitled
5
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project.name
0 Stars     55 Views
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User Image Suryamani Sudhakar 1270

2*4 Decoder

2*4 Decoder
F(A B C)=SUM[1 3 5 6]
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project.name
0 Stars     82 Views
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User Image Júlia Almeida Luna

2Lista

2Lista
Ex 2 4 5 6
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project.name
0 Stars     81 Views
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User Image Adrian Tuazon

Activity 3

Activity 3
1 2 3 4 5
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project.name
0 Stars     40 Views
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User Image Christopher Fernand0

ACTIVITY 4

ACTIVITY 4
5
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project.name
0 Stars     21 Views
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User Image namrata_30115

NAMRATA

NAMRATA
EX 5
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project.name
0 Stars     34 Views
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User Image Vidhi

41_Vidhi_Logic Gates_(NOT)

41_Vidhi_Logic Gates_(NOT)
5
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project.name
0 Stars     70 Views
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User Image Chirag

21UCS051_Exp9

21UCS051_Exp9
5
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project.name
0 Stars     18 Views
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User Image Andre Magtibay

5

5
5
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project.name
0 Stars     11 Views
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User Image susaan shrestha

verification of boolean law

verification of boolean law
5
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berification of boolean law

project.name
0 Stars     13 Views
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User Image A_MOHAMED_MAHIN_AYAS

mod 5 synchronous updown counter

mod 5 synchronous updown counter
mod 5
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project.name
0 Stars     18 Views
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User Image Rakshitha

exp 2

exp 2
5 6
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adder,subtraction

project.name
0 Stars     14 Views
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User Image Rakshitha

OR gate using NOR gate

OR gate using NOR gate
5
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transformation  of NOR Gate into OR Gate

project.name
0 Stars     12 Views
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User Image Rakshitha

AND Gate using NOR Gate

AND Gate using NOR Gate
5
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Transformation of NOR Gate AND Gate

project.name
0 Stars     20 Views
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User Image Rakshitha

EXP 4...encoder and decoder logic circuits

EXP 4...encoder and decoder logic circuits
9 5
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encoder and decoder

project.name
0 Stars     20 Views
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User Image Rakshitha

2 to 4 decoder

2 to 4 decoder
8 5
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decoder

project.name
0 Stars     17 Views
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User Image Rakshitha

exp 5: design of logic diagram using NAND gates

exp 5: design of logic diagram using NAND gates
5 2
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exp 5-using NAND Gates

project.name
0 Stars     12 Views
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User Image Rakshitha

EXP 6: JK Flip-flop implementation using nand gate

EXP 6: JK Flip-flop implementation using nand gate
5
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LEVEL 2

project.name
0 Stars     24 Views
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User Image Dipanshi Maurya 22220CMP007

Assignment4

Assignment4
Q.1 2 3 4 5
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project.name
0 Stars     35 Views
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User Image Miguel Arnold

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7
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his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent

project.name
0 Stars     26 Views
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User Image Suraj B

question 4

question 4
4. Design a combinational circuit with three inputs x y z and three outputs A B C. When the binary input is 0 1 2 or 3 the binary output is one greater than the input. When the binary input is 4 5 6 or 7 the binary output is one less than the input.
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project.name
0 Stars     40 Views
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User Image Gustavo Ortiz

Mapas K (5 bits)

Mapas K (5 bits)
F(ABCDE)={18 29 5 31 10 21 14 3 7 26 16 1 9 23 28 12 6 0 20 17 30 11 25 4 19}
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project.name
0 Stars     33 Views
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User Image Kavay Gupta

NAND Circuit diagram

NAND Circuit diagram
nand 5 gates
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project.name
0 Stars     5 Views
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User Image K Priya

exp-5 continue

exp-5 continue
5
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project.name
0 Stars     4 Views
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User Image Srikanth svs

BINARY TO GRAY CODE

BINARY TO GRAY CODE
4 5
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project.name
0 Stars     3 Views
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User Image k Guru teja

Untitled

Untitled
5
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project.name
0 Stars     3 Views
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User Image anotony kenson

verification of logic gates 5

verification of logic gates 5
5
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project.name
0 Stars     3 Views
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User Image anotony kenson

verification of boolean laws5

verification of boolean laws5
5
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project.name
0 Stars     3 Views
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User Image Mohammed Azeemulla Khan

Commutative Law

Commutative Law
5
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