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project.name
0 Stars     105 Views
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User Image Iris Rocio Curo Quispe

prepract

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project.name
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User Image Iris Rocio Curo Quispe

Untitled

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project.name
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User Image Iris Rocio Curo Quispe

semisumador 1

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project.name
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User Image Iris Rocio Curo Quispe

full adder

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project.name
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User Image Iris Rocio Curo Quispe

sumador completo

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project.name
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User Image Iris Rocio Curo Quispe

UAL de 2 bit

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project.name
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User Image Harshit Agarwal

HARSHIT

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project.name
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User Image дмитрий красножен

pract3

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project.name
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User Image 1960627 NIKHIL GUPTA

Experiment 1

1 2a 2b 3 4a 4b 5 6 7a 7b 8 9
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NIKHIL GUPTA 

1960627

project.name
1 Stars     46 Views
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User Image D_2061008_M.Maria Anish

experement 2 2,3,4,5, question 2061008

question 2 3 4 5
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 question no ; 2,3,4,5

project.name
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User Image David Alejandro Sandoval Luna

3 bit counter

3 bit counter 3bitcounter
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3 bit counter

project.name
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User Image janjua

janjuas project

1 3
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project.name
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User Image Rishika

4 X 1 MULTIPLEXER

3
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project.name
1 Stars     44 Views
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User Image MAYANK AGRAWAL

Practical 3

COA practical file 3
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AIM : IMPLEMENT 3-BIT PARALLEL BINARY ADDER/SUBTRACTOR

project.name
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User Image PRAMOD PANDEY

practical 3

COA practical file 3 pramod
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AIM:IMPLEMENT 3BIT PARALLEL BINARY ADDER/SUBTRACTOR

project.name
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User Image Anil03

logic gates

3
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project.name
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User Image Suryamani Sudhakar 1270

2*4 Decoder

F(A B C)=SUM[1 3 5 6]
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project.name
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User Image Akrm Youssef

Practical assignment 3

3
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project.name
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User Image Adrian Tuazon

Activity 3

1 2 3 4 5
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project.name
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User Image Saurabh Gupta

DSD Lab Assignment 2 (Task #3) - 3 Bit Magnitude Comparator

magnitude comparator greater smaller equal 3 bit magnitude comparator 3 bit saurabh gupta
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project.name
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User Image Swarit30172

assignment3

circuit 3
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project.name
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User Image Christopher Fernand0

ACT 4

3
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project.name
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User Image S Meenakshi

S MEENAKSHI

3
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project.name
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User Image sana

HW6

3 4
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shoo

project.name
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User Image Vidhi

41_Vidhi Prajapati_Logic Gates (AND)

3
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project.name
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User Image Tarun Bansal

DC Lab

1 2 3 4
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project.name
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21UCS051_Exp9

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project.name
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User Image Andre Magtibay

3

3
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project.name
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User Image 鄭立姸

3

3
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project.name
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User Image ADITYA CHAURASIA

Implementing 3-8 line DECODER

3
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project.name
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User Image Rakshitha

full subtractor

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full subtractor

project.name
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User Image A

Untitled

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project.name
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User Image Dhrithi

JK flip flop implementation using NAND gate

3
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Experiment 6

Level 2

project.name
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User Image Dhrithi

D,T,SR,JK Flip flop

1 2 3 4
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Experiment 6

Level 1

project.name
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User Image Dipanshi Maurya 22220CMP007

Assignment4

Q.1 2 3 4 5
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