project.name

Mandar Uday Patil

Member since: 3 years

Educational Institution: visvesvaraya national institute of technolgy

Country: India

4 bit shift register

4 bit shift register
Public
project.name

verification of de morgan law

verification of de morgan law
Public
project.name

Subtracter circuit

Subtracter circuit
Public
project.name

4 bit shift bidirectional circuit

4 bit shift bidirectional circuit
Public
project.name

Implement using minimum number NAND gate

Implement using minimum number NAND gate
Public
project.name

Adder circuit

Adder circuit
Public
project.name

Master Slave JK Flip-flop

Master Slave JK Flip-flop
Public
project.name

Study of AND, OR , NOT , XOR , NAND and NOR gate

Study of AND, OR , NOT , XOR , NAND and NOR gate
Public
project.name

To design the majority gate

To design the majority gate
Public
project.name

Implement the Boolean function using NAND gate

Implement the Boolean function using NAND gate
Public
project.name

Implement using minimum number NAND gate

Implement using minimum number NAND gate
Public
project.name

8:1 multiplexer

8:1 multiplexer
Public
project.name

verfication of truth table of all gates

verfication of truth table of all gates
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

3:8 decoder

3:8 decoder
Public
project.name

T & D flip flops using JK flip flops

T & D flip flops using JK flip flops
Public
project.name

verfiy J-K flip flop and implement master Slave condition using JK Flip Flop

verfiy J-K flip flop and implement master Slave condition using JK Flip Flop
Public
project.name
No result image
Mandar Uday Patil doesn't have any favourites.

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name