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Mandar Uday Patil

Member since: 3 years

Educational Institution: visvesvaraya national institute of technolgy

Country: India

4 bit shift register

4 bit shift register
Public
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verification of de morgan law

verification of de morgan law
Public
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Subtracter circuit

Subtracter circuit
Public
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4 bit shift bidirectional circuit

4 bit shift bidirectional circuit
Public
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Implement using minimum number NAND gate

Implement using minimum number NAND gate
Public
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Adder circuit

Adder circuit
Public
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Master Slave JK Flip-flop

Master Slave JK Flip-flop
Public
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Study of AND, OR , NOT , XOR , NAND and NOR gate

Study of AND, OR , NOT , XOR , NAND and NOR gate
Public
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To design the majority gate

To design the majority gate
Public
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4 bit bidirectional shift register

4 bit bidirectional shift register
Public
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Implement the Boolean function using NAND gate

Implement the Boolean function using NAND gate
Public
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Implement using minimum number NAND gate

Implement using minimum number NAND gate
Public
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8:1 multiplexer

8:1 multiplexer
Public
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verfication of truth table of all gates

verfication of truth table of all gates
Public
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4 bit bidirectional shift register

4 bit bidirectional shift register
Public
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verfiy J-K flip flop and implement master Slave condition using JK Flip Flop

verfiy J-K flip flop and implement master Slave condition using JK Flip Flop
Public
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T & D flip flops using JK flip flops

T & D flip flops using JK flip flops
Public
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3:8 decoder

3:8 decoder
Public
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4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name