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Dhrithi

Member since: 1 year

Educational Institution: Presidency University , Banglore.

Country: India

Untitled

Untitled
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2 to 4 decoder

2 to 4 decoder
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4 to 2 decoder

4 to 2 decoder
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1 to 4 DE-Multiplexer

1 to 4 DE-Multiplexer
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EXPT:07

EXPT:07
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Half subtractor using XOR and NAND

Half subtractor using XOR and NAND
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Half adder using XOR and NAND

Half adder using XOR and NAND
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Full Subtractor using XOR and NAND

Full Subtractor using XOR and NAND
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Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
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Transformation of NAND gate into NOT,OR and AND gates

Transformation of NAND gate into NOT,OR and AND gates
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3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
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EXP8

EXP8
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2 to 1 DEMUX

2 to 1 DEMUX
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3 bit Full subtractor using NAND gate

3 bit Full subtractor using NAND gate
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3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
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Design of Logic Diagram using NAND gate-exp 5

Design of Logic Diagram using NAND gate-exp 5
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Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
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4 to 2 Priority encoder

4 to 2 Priority encoder
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D to JK flip flop conversion

D to JK flip flop conversion
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JK to D flip flop implementation using NAND gate

JK to D flip flop implementation using NAND gate
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2:1 MUX using universal gate

2:1 MUX using universal gate
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4:1 MUX using universal gates

4:1 MUX using universal gates
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D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
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1 to 2 DEMUX

1 to 2 DEMUX
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Basic logic gates

Basic logic gates
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Transformation of nor gate into AND gate

Transformation of nor gate into AND gate
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JK to D flip flop conversion

JK to D flip flop conversion
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4 to 1 DEMUX

4 to 1 DEMUX
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4 to 2 Priority encoder

4 to 2 Priority encoder
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Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
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JK flip flop implementation using NAND gate

JK flip flop implementation using NAND gate
Public
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4 to 1 MUX

4 to 1 MUX
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Full adder using XOR and NAND

Full adder using XOR and NAND
Public
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2 to 1 multiplexer

2 to 1 multiplexer
Public
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3 bit half subtractor using NAND gate

3 bit half subtractor using NAND gate
Public
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