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Dhrithi

Member since: 9 months

Educational Institution: Presidency University , Banglore.

Country: India

Untitled

Untitled
Public
Untitled

4 to 2 Priority encoder

4 to 2 Priority encoder
Public
4 to 2 Priority encoder

2 to 4 decoder

2 to 4 decoder
Public
2 to 4 decoder

4 to 2 decoder

4 to 2 decoder
Public
4 to 2 decoder

Half subtractor using XOR and NAND

Half subtractor using XOR and NAND
Public
Half subtractor using XOR and NAND

Half adder using XOR and NAND

Half adder using XOR and NAND
Public
Half adder using XOR and NAND

Full Subtractor using XOR and NAND

Full Subtractor using XOR and NAND
Public
Full Subtractor using XOR and NAND

Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
Public
Transformation of nor gate into NOT and OR gate

Transformation of NAND gate into NOT,OR and AND gates

Transformation of NAND gate into NOT,OR and AND gates
Public
Transformation of NAND gate into NOT,OR and AND gates

3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
Public
3 bit Full adder using NAND gate

EXP8

EXP8
Public
EXP8

2 to 1 DEMUX

2 to 1 DEMUX
Public
2 to 1 DEMUX

EXPT:07

EXPT:07
Public
EXPT:07

4 to 1 MUX

4 to 1 MUX
Public
4 to 1 MUX

1 to 4 DE-Multiplexer

1 to 4 DE-Multiplexer
Public
1 to 4 DE-Multiplexer

4 to 1 DEMUX

4 to 1 DEMUX
Public
4 to 1 DEMUX

3 bit Full subtractor using NAND gate

3 bit Full subtractor using NAND gate
Public
3 bit Full subtractor using NAND gate

3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
Public
3 bit half adder uising NAND gate

3 bit half subtractor using NAND gate

3 bit half subtractor using NAND gate
Public
3 bit half subtractor using NAND gate

Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
Public
Realization of 2:1 MUX using Basic and XOR gate

Design of Logic Diagram using NAND gate-exp 5

Design of Logic Diagram using NAND gate-exp 5
Public
Design of Logic Diagram using NAND gate-exp 5

Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
Public
Design of logic diagram using basic gates on online simulator-exp 5

4 to 2 Priority encoder

4 to 2 Priority encoder
Public
4 to 2 Priority encoder

D to JK flip flop conversion

D to JK flip flop conversion
Public
D to JK flip flop conversion

JK to D flip flop conversion

JK to D flip flop conversion
Public
JK to D flip flop conversion

JK flip flop implementation using NAND gate

JK flip flop implementation using NAND gate
Public
JK flip flop implementation using NAND gate

JK to D flip flop implementation using NAND gate

JK to D flip flop implementation using NAND gate
Public
JK to D flip flop implementation using NAND gate

2:1 MUX using universal gate

2:1 MUX using universal gate
Public
2:1 MUX using universal gate

4:1 MUX using universal gates

4:1 MUX using universal gates
Public
4:1 MUX using universal gates

D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
Public
D,T,SR,JK Flip flop

2 to 1 multiplexer

2 to 1 multiplexer
Public
2 to 1 multiplexer

1 to 2 DEMUX

1 to 2 DEMUX
Public
1 to 2 DEMUX

Full adder using XOR and NAND

Full adder using XOR and NAND
Public
Full adder using XOR and NAND

Basic logic gates

Basic logic gates
Public
Basic logic gates

Transformation of nor gate into AND gate

Transformation of nor gate into AND gate
Public
Transformation of nor gate into AND gate
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