Untitled

D,T,SR,JK Flip flop

2 to 4 decoder

4 to 2 decoder

1 to 4 DE-Multiplexer

EXPT:07

Half subtractor using XOR and NAND

Half adder using XOR and NAND

Full Subtractor using XOR and NAND

Transformation of nor gate into NOT and OR gate

Transformation of NAND gate into NOT,OR and AND gates

3 bit Full adder using NAND gate

EXP8

2 to 1 DEMUX

3 bit Full subtractor using NAND gate

3 bit half adder uising NAND gate

Design of Logic Diagram using NAND gate-exp 5

4 to 2 Priority encoder

D to JK flip flop conversion

JK to D flip flop implementation using NAND gate

2:1 MUX using universal gate

1 to 2 DEMUX

Basic logic gates

Transformation of nor gate into AND gate

JK to D flip flop conversion

4 to 1 DEMUX

4 to 2 Priority encoder

Realization of 2:1 MUX using Basic and XOR gate

Full adder using XOR and NAND

2 to 1 multiplexer

JK flip flop implementation using NAND gate

4:1 MUX using universal gates

3 bit half subtractor using NAND gate

4 to 1 MUX

Design of logic diagram using basic gates on online simulator-exp 5