**Member since:** 1 year

**Educational Institution:** Presidency University , Banglore.

**Country:** India

Untitled

Untitled
Public

2 to 4 decoder

2 to 4 decoder
Public

4 to 2 decoder

4 to 2 decoder
Public

1 to 4 DE-Multiplexer

1 to 4 DE-Multiplexer
Public

EXPT:07

EXPT:07
Public

Half subtractor using XOR and NAND

Half subtractor using XOR and NAND
Public

Half adder using XOR and NAND

Half adder using XOR and NAND
Public

Full Subtractor using XOR and NAND

Full Subtractor using XOR and NAND
Public

Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
Public

Transformation of NAND gate into NOT,OR and AND gates

Transformation of NAND gate into NOT,OR and AND gates
Public

3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
Public

EXP8

EXP8
Public

2 to 1 DEMUX

2 to 1 DEMUX
Public

3 bit Full subtractor using NAND gate

3 bit Full subtractor using NAND gate
Public

3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
Public

Design of Logic Diagram using NAND gate-exp 5

Design of Logic Diagram using NAND gate-exp 5
Public

Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
Public

4 to 2 Priority encoder

4 to 2 Priority encoder
Public

D to JK flip flop conversion

D to JK flip flop conversion
Public

JK to D flip flop implementation using NAND gate

JK to D flip flop implementation using NAND gate
Public

2:1 MUX using universal gate

2:1 MUX using universal gate
Public

4:1 MUX using universal gates

4:1 MUX using universal gates
Public

D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
Public

1 to 2 DEMUX

1 to 2 DEMUX
Public

Basic logic gates

Basic logic gates
Public

Transformation of nor gate into AND gate

Transformation of nor gate into AND gate
Public

JK to D flip flop conversion

JK to D flip flop conversion
Public

4 to 1 DEMUX

4 to 1 DEMUX
Public

4 to 2 Priority encoder

4 to 2 Priority encoder
Public

Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
Public

JK flip flop implementation using NAND gate

JK flip flop implementation using NAND gate
Public

4 to 1 MUX

4 to 1 MUX
Public

Full adder using XOR and NAND

Full adder using XOR and NAND
Public

2 to 1 multiplexer

2 to 1 multiplexer
Public

3 bit half subtractor using NAND gate

3 bit half subtractor using NAND gate
Public