Searched Projects

Tags: 1

project.name
0 Stars     100 Views
User:
User Image Moises Alberto Salazar Machaca

Prueba

Prueba
1
View
project.name
0 Stars     125 Views
User:
User Image Iris Rocio Curo Quispe

practica1

practica1
1
View
project.name
0 Stars     146 Views
User:
User Image Iris Rocio Curo Quispe

borrador1

borrador1
1
View
project.name
0 Stars     171 Views
User:
User Image Iris Rocio Curo Quispe

MULTIPLEXOR 4 X 1

MULTIPLEXOR 4 X 1
1
View
project.name
0 Stars     142 Views
User:
User Image Iris Rocio Curo Quispe

Circuito secuencial

Circuito secuencial
1
View
project.name
0 Stars     161 Views
User:
User Image Iris Rocio Curo Quispe

distancia h

distancia h
1
View
project.name
0 Stars     156 Views
User:
User Image Iris Rocio Curo Quispe

surc

surc
1
View
project.name
0 Stars     154 Views
User:
User Image Harshit Agarwal

HARSHIT

HARSHIT
1
View
project.name
0 Stars     131 Views
User:
User Image cont cont

1

1
1
View
project.name
0 Stars     117 Views
User:
User Image milagros

ejercicio3.ALU

ejercicio3.ALU
1
View
project.name
0 Stars     105 Views
User:
User Image Amin

csa1

csa1
1
View
project.name
0 Stars     139 Views
User:
User Image дмитрий красножен

pract1

pract1
1
View
project.name
0 Stars     116 Views
User:
User Image AISAH_ 243

lat3

lat3
1
View
project.name
0 Stars     104 Views
User:
User Image Andrej

Matrich

Matrich
1
View
project.name
0 Stars     106 Views
User:
User Image AISAH_ 243

1

1
1
View
project.name
0 Stars     124 Views
User:
User Image дмитрий красножен

Store inf

Store inf
1
View
project.name
0 Stars     133 Views
User:
User Image Илья Да так-то

Инфа

Инфа
1
View
ымсвы
project.name
0 Stars     147 Views
User:
User Image Mishi Shah

ring counter

ring counter
1
View
dld
project.name
0 Stars     104 Views
User:
User Image louis

circuit 1

circuit 1
1
View
project.name
0 Stars     110 Views
User:
User Image louis

louis

louis
1
View
project.name
0 Stars     88 Views
User:
User Image chengch

1

1
1
View
project.name
0 Stars     87 Views
User:
User Image Szymon Zacharow

Sprawdzian Eutk

Sprawdzian Eutk
1
View
project.name
0 Stars     80 Views
User:
User Image سوير ال رشيد

3*8

3*8
1
View
project.name
0 Stars     80 Views
User:
User Image Yefry Sajquiy

Circuito caracol

Circuito caracol
1
View

cicuito caracol lectura 1101

project.name
0 Stars     85 Views
User:
User Image Anfas Walker

De-Morgan’s Law using two variables.

De-Morgan’s Law using two variables.
1
View
project.name
0 Stars     86 Views
User:
User Image Miguel

TP4 -1

TP4 -1
1
View
project.name
0 Stars     78 Views
User:
User Image sergio galindo

AND

AND
1
View
project.name
0 Stars     80 Views
User:
User Image Ayça

Ayça

Ayça
1
View
project.name
0 Stars     84 Views
User:
User Image 1960627 NIKHIL GUPTA

Experiment 1

Experiment 1
1 2a 2b 3 4a 4b 5 6 7a 7b 8 9
View

NIKHIL GUPTA 

1960627

project.name
0 Stars     104 Views
User:
User Image Sharun E Rajeev

Experiment 1

Experiment 1
1
View

My first experiment in DE lab.

project.name
0 Stars     74 Views
User:
User Image RUAAYAH

EX3

EX3
1
View
project.name
0 Stars     89 Views
User:
User Image LUCAS HENRIQUE MANHANI

not

not
1
View
project.name
0 Stars     63 Views
User:
User Image berdnikov127

1 project

1 project
1
View

1

project.name
0 Stars     67 Views
User:
User Image saurabh kumar

xor 1

xor 1
1
View

[email protected]

project.name
0 Stars     104 Views
User:
User Image Nanditha AM

1 Circuit

1 Circuit
1 circuit
View

XY'+(X+Y)'=A

project.name
0 Stars     760 Views
User:
User Image Stephany Merari Fuentes Sierra

Entregable

Entregable
Entregable 1
View

Primer entregable parcial

project.name
0 Stars     85 Views
User:
User Image janjua

janjuas project

janjuas project
1 3
View
project.name
0 Stars     49 Views
User:
User Image Chitanu Victor

Lab1

Lab1
1
View
project.name
0 Stars     63 Views
User:
User Image Chennuru sai sadvika reddy 4018

CODE CONVERTOR

CODE CONVERTOR
1
View
project.name
0 Stars     121 Views
User:
User Image HellSpecter

multiplexor

multiplexor
1
View
project.name
0 Stars     59 Views
User:
User Image Avinash Saroj

test

test
1
View
project.name
0 Stars     63 Views
User:
User Image chan

j

j
1
View
project.name
0 Stars     57 Views
User:
User Image Erik

CircuitVerse

CircuitVerse
1
View
project.name
0 Stars     61 Views
User:
User Image НeIzVeStn0sTb

Untitled

Untitled
1
View

111

project.name
0 Stars     82 Views
User:
User Image niraj kumar

NIRAJ DE

NIRAJ DE
DE 1
View
project.name
0 Stars     52 Views
User:
User Image nikesh v

lab 6

lab 6
1
View
project.name
0 Stars     60 Views
User:
User Image Christian Alejandro Sarmiento Sánchez

memoria

memoria
1
View

memoria digitales 2

project.name
0 Stars     52 Views
User:
User Image Miguel Ángel Medina Arellanes

Untitled

Untitled
1
View
project.name
0 Stars     53 Views
User:
User Image HRISHIK SANCHETI

Expt1

Expt1
1
View
project.name
0 Stars     84 Views
User:
User Image Adrian Tuazon

Activity 3

Activity 3
1 2 3 4 5
View
project.name
0 Stars     51 Views
User:
User Image Diyora Botirova

LAB1

LAB1
1
View
project.name
0 Stars     48 Views
User:
User Image Khadichabonu

Logic Gates

Logic Gates
1
View

14 september 2021 year


project.name
0 Stars     56 Views
User:
User Image Abhinav

Half and Full Adder

Half and Full Adder
1
View
project.name
0 Stars     53 Views
User:
User Image Akash Dubey

Untitled

Untitled
1
View


project.name
0 Stars     73 Views
User:
User Image Christopher Fernand0

ACTIVITY 4

ACTIVITY 4
1
View
project.name
0 Stars     53 Views
User:
User Image syed Izhar Ali

7 sagment displays

7 sagment displays
1
View
project.name
0 Stars     76 Views
User:
User Image ismail

lab 1

lab 1
lab 1
View
project.name
0 Stars     55 Views
User:
User Image Naveen

naveen

naveen
1
View
project.name
0 Stars     17 Views
User:
User Image Nam Ngô Hoài

Nam

Nam
1
View
project.name
0 Stars     28 Views
User:
User Image loges sivarman

lOGES

lOGES
1
View
project.name
0 Stars     33 Views
User:
User Image asif khan

10

10
1
View
project.name
0 Stars     75 Views
User:
User Image Ahmed hamoda l Ali marey

AHMED HAMODA

AHMED HAMODA
1
View
project.name
0 Stars     70 Views
User:
User Image Keenan

13-1

13-1
13 1
View

13,1

project.name
0 Stars     53 Views
User:
User Image Hoara

Informatik 1

Informatik 1
1
View
project.name
0 Stars     87 Views
User:
User Image Tarun Bansal

DC Lab

DC Lab
1 2 3 4
View
project.name
0 Stars     64 Views
User:
User Image 20bcs011 Hitesh vashisth

lab assignment

lab assignment
1
View
project.name
0 Stars     60 Views
User:
User Image Talal

KSA

KSA
1
View
project.name
0 Stars     21 Views
User:
User Image YANALA ABHINAY REDDY

DEMORGANS LAW

DEMORGANS LAW
1
View
project.name
0 Stars     57 Views
User:
User Image Piero

trab final

trab final
1
View
project.name
0 Stars     47 Views
User:
User Image Chirag

21UCS051_Exp9

21UCS051_Exp9
1
View
project.name
0 Stars     46 Views
User:
User Image Nath pushkar

Half Adder

Half Adder
Half adder 1
View
project.name
0 Stars     87 Views
User:
User Image Nath pushkar

Half adder

Half adder
Half adder 1
View
project.name
0 Stars     52 Views
User:
User Image Alp Tuğrul Akşam

Untitled

Untitled
#3 1
View
project.name
0 Stars     63 Views
User:
User Image Didier Mtz Rdz

Didier Circuito

Didier Circuito
Circuito 1
View
project.name
1 Stars     52 Views
User:
User Image Daniel Mamani Ramos

Tarea lab Sis. digitales

Tarea lab Sis. digitales
1
View
project.name
0 Stars     52 Views
User:
User Image Muhamad Taruna Pramudhita

20524068_Muhamad Taruna_1

20524068_Muhamad Taruna_1
SISDIG 1
View
project.name
0 Stars     61 Views
User:
User Image Muhamad Taruna Pramudhita

20524068_Muhamad Taruna_2

20524068_Muhamad Taruna_2
SISDIG 1
View
project.name
0 Stars     52 Views
User:
User Image vikashsharma

SKILL BASED MINI PROJECT

SKILL BASED MINI PROJECT
1
View
project.name
0 Stars     14 Views
User:
User Image vikashsharma

SKILL BASED NANDINI

SKILL BASED NANDINI
1
View
project.name
0 Stars     51 Views
User:
User Image Abdul Wahid

decoder

decoder
1
View
project.name
0 Stars     63 Views
User:
User Image shaik munawar

shaik munawar,20211csg0072

shaik munawar,20211csg0072
experiment 1
View
project.name
0 Stars     12 Views
User:
User Image Pragya Mittal

full adder

full adder
1
View
project.name
0 Stars     15 Views
User:
User Image Jeisson fabian Torres contreras

punto 1 taller 2

punto 1 taller 2
1
View
project.name
0 Stars     26 Views
User:
User Image Andre Magtibay

2

2
1
View
project.name
0 Stars     12 Views
User:
User Image Michael Powell

Michael Powell - CircuitVerse_CSX_1

Michael Powell - CircuitVerse_CSX_1
CSX 1
View

This circuit determines if two triangles are congruent given a set of six inputs relating the triangles' side lengths and angle measures.

project.name
0 Stars     11 Views
User:
User Image muneeraibraheem

Untitled1

Untitled1
1
View
project.name
0 Stars     11 Views
User:
User Image 吳尚哲

Untitled

Untitled
1
View
project.name
0 Stars     9 Views
User:
User Image 727821TUEC122 MONIKA SRI B.

RS flipflop

RS flipflop
1
View

rs flipflop

project.name
0 Stars     13 Views
User:
User Image 727821TUEC124 NANDITHA V.

RS FLIPFLOP

RS FLIPFLOP
1
View
project.name
0 Stars     13 Views
User:
User Image Mustafa Can Buyuksari

Untitled1

Untitled1
1
View
project.name
0 Stars     43 Views
User:
User Image TelAviv

seven segment

seven segment
logic 1
View
project.name
0 Stars     12 Views
User:
User Image Peyton McCarrick

Project 1

Project 1
1
View
project.name
0 Stars     9 Views
User:
User Image arpit pandey

piso

piso
1
View
project.name
0 Stars     11 Views
User:
User Image Navya Arveti

experiment 1

experiment 1
1
View
project.name
0 Stars     16 Views
User:
User Image Dhrithi

Half adder using XOR and NAND

Half adder using XOR and NAND
1
View

Experiment 2

Level 1


project.name
0 Stars     17 Views
User:
User Image Dhrithi

Full adder using XOR and NAND

Full adder using XOR and NAND
1
View

Experiment 2

Level 1


project.name
0 Stars     20 Views
User:
User Image Rakshitha

half subtractor using XOR and NANAD Gates

half subtractor using XOR and NANAD Gates
1
View

half subtractor

project.name
0 Stars     19 Views
User:
User Image Dhrithi

Transformation of nor gate into NOT and OR gate

Transformation of nor gate into NOT and OR gate
1 2
View

Experiment 1

Level 2


project.name
0 Stars     12 Views
User:
User Image PAVANI AMMU

20221CBD0014

20221CBD0014
1
View
project.name
0 Stars     19 Views
User:
User Image Dhrithi

3 bit Full adder using NAND gate

3 bit Full adder using NAND gate
1
View

Level 2


project.name
0 Stars     18 Views
User:
User Image Dhrithi

3 bit half adder uising NAND gate

3 bit half adder uising NAND gate
1
View

Level 2

project.name
0 Stars     22 Views
User:
User Image Dhrithi

Realization of 2:1 MUX using Basic and XOR gate

Realization of 2:1 MUX using Basic and XOR gate
1
View

Logic circuit of 2-to-1 Multiplexer

project.name
0 Stars     10 Views
User:
User Image PAVANI AMMU

20221CBD0014

20221CBD0014
1
View
project.name
0 Stars     15 Views
User:
User Image Dhrithi

2 to 1 multiplexer

2 to 1 multiplexer
1
View

Realization of 2 to 1 MUX using basic and XOR gate

project.name
0 Stars     16 Views
User:
User Image Dhrithi

1 to 2 DEMUX

1 to 2 DEMUX
1
View

DEMUX

project.name
0 Stars     16 Views
User:
User Image Dhrithi

2 to 1 DEMUX

2 to 1 DEMUX
1
View

By using universal gate


project.name
0 Stars     14 Views
User:
User Image Dhrithi

4 to 2 decoder

4 to 2 decoder
1
View

Encoder and Decoder logic gates

project.name
0 Stars     18 Views
User:
User Image Dhrithi

4 to 2 Priority encoder

4 to 2 Priority encoder
1
View

Priority encoder

project.name
0 Stars     22 Views
User:
User Image Rakshitha

LEVEL 2: Priority encoder

LEVEL 2: Priority encoder
1
View

A:2 Priority encoder

project.name
0 Stars     15 Views
User:
User Image Dhrithi

Design of logic diagram using basic gates on online simulator-exp 5

Design of logic diagram using basic gates on online simulator-exp 5
1
View

Experiment 5

level 1

project.name
0 Stars     11 Views
User:
User Image Dhrithi

D to JK flip flop conversion

D to JK flip flop conversion
1
View

Experiment 6

Level 2

project.name
0 Stars     23 Views
User:
User Image Rakshitha

level 2:exp 6 JK To D Flip-flop conversion

level 2:exp 6 JK To D Flip-flop conversion
1 6
View

JK TO D FLIP-FLOP CONVERSION

project.name
0 Stars     22 Views
User:
User Image Dhrithi

D,T,SR,JK Flip flop

D,T,SR,JK Flip flop
1 2 3 4
View

Experiment 6

Level 1

project.name
0 Stars     12 Views
User:
User Image Phan Thanh Bảo

CEA

CEA
1
View
project.name
0 Stars     40 Views
User:
User Image Miguel Arnold

GATE VERIFICATION

GATE VERIFICATION
1 2 3 4 5 6 7
View

his is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. 

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represent

project.name
0 Stars     27 Views
User:
User Image ekaksh mishra

To study and verify logic gates

To study and verify logic gates
experiment 1
View

experiment no 1

project.name
0 Stars     23 Views
User:
User Image ekaksh mishra

To study and verify logic gates

To study and verify logic gates
experiment 1
View
project.name
0 Stars     13 Views
User:
User Image Mufeez Ali

mufeez project 1

mufeez project 1
1
View
project.name
0 Stars     29 Views
User:
User Image Suraj B

question 4

question 4
4. Design a combinational circuit with three inputs x y z and three outputs A B C. When the binary input is 0 1 2 or 3 the binary output is one greater than the input. When the binary input is 4 5 6 or 7 the binary output is one less than the input.
View
project.name
0 Stars     45 Views
User:
User Image Gustavo Ortiz

Mapas K (5 bits)

Mapas K (5 bits)
F(ABCDE)={18 29 5 31 10 21 14 3 7 26 16 1 9 23 28 12 6 0 20 17 30 11 25 4 19}
View
project.name
0 Stars     14 Views
User:
User Image Bhavani Satish Kumar

Basic gates

Basic gates
1 2 at
View
project.name
0 Stars     17 Views
User:
User Image Raushan Yadav

Raushan Yadav

Raushan Yadav
1
View

complete gate project

project.name
0 Stars     8 Views
User:
User Image Saishree N

Untitled1

Untitled1
1
View
project.name
0 Stars     15 Views
User:
User Image Madhu sudhan

Untitled

Untitled
EXPERIMENT 1
View
project.name
0 Stars     13 Views
User:
User Image Chahat Singh

titled

titled
1
View
project.name
0 Stars     11 Views
User:
User Image Jagdeesh Kumar Pal

assingment1

assingment1
1
View
project.name
0 Stars     9 Views
User:
User Image VISHWANATH JOSHI

exp-3

exp-3
1
View
project.name
0 Stars     14 Views
User:
User Image huang1234399

Untitled

Untitled
1
View

first

project.name
0 Stars     17 Views
User:
User Image Prince Mapumah

lab4

lab4
1 2
View
project.name
0 Stars     18 Views
User:
User Image Prince Mapumah

lab4

lab4
2 1
View
project.name
0 Stars     18 Views
User:
User Image Prince Mapumah

lab4

lab4
1 2
View
project.name
0 Stars     18 Views
User:
User Image Rahma Fitri Annisa

Untitled

Untitled
1 4 7
View
project.name
0 Stars     13 Views
User:
User Image Toka

Untitled

Untitled
1 2
View
project.name
0 Stars     11 Views
User:
User Image Aline Brincker

Digitale Logik

Digitale Logik
1
View
project.name
0 Stars     7 Views
User:
User Image vansh

multiplexer

multiplexer
1
View
project.name
0 Stars     10 Views
User:
User Image Nikola Gaborov

1

1
1
View

8 segment

project.name
0 Stars     15 Views
User:
User Image Pandu Ari Wijaya

ENCODER

ENCODER
1
View
project.name
0 Stars     10 Views
User:
User Image Luis Leonardo

Ej 1

Ej 1
Ej 1
View
project.name
0 Stars     11 Views
User:
User Image Prof Narendra Kumar

1

1
1
View
project.name
0 Stars     33 Views
User:
User Image Steve

Steve B. Badayos

Steve B. Badayos
t I n G S 1 2 h
View
project.name
0 Stars     42 Views
User:
User Image Renz Labao

MATT DANIEL PEPINO

MATT DANIEL PEPINO
g H o S t Y 1 8
View
project.name
0 Stars     8 Views
User:
User Image Daniel Dressel

Nr.6

Nr.6
1
View
project.name
0 Stars     9 Views
User:
User Image Gabriel

Untitled

Untitled
1
View
project.name
0 Stars     12 Views
User:
User Image divyashree

Untitled

Untitled
1
View
project.name
0 Stars     13 Views
User:
User Image S.B. Veeranna

NOT Gate

NOT Gate
1
View
project.name
0 Stars     8 Views
User:
User Image Vlad_PN

Мультиплексори та демультиплексори.

Мультиплексори та демультиплексори.
1
View
project.name
0 Stars     7 Views
User:
User Image Russ Gebrengus

Untitled

Untitled
1
View

class work creating a circuit sympols 

project.name
0 Stars     8 Views
User:
User Image Keerti Neeramanigar

Keerti N1

Keerti N1
1
View
project.name
0 Stars     7 Views
User:
User Image Gangapalli Pallavi

Untitled

Untitled
1
View
project.name
0 Stars     7 Views
User:
User Image L GURU KIRAN

Untitled

Untitled
1
View
project.name
0 Stars     9 Views
User:
User Image SHREYAS S RAMAN

EXPT 02

EXPT 02
1
View
project.name
0 Stars     7 Views
User:
User Image Ruchi

S R Flip-Flop using NAND Gate

S R Flip-Flop using NAND Gate
1
View
project.name
0 Stars     6 Views
User:
User Image Maryam Alfraidy

Untitled

Untitled
1
View
project.name
0 Stars     6 Views
User:
User Image jahnavi

Untitled

Untitled
1
View
project.name
0 Stars     7 Views
User:
User Image jahnavi

4*1 multiplexer

4*1 multiplexer
1
View
project.name
0 Stars     8 Views
User:
User Image jahnavi

8*1 mul;tiplexer

8*1 mul;tiplexer
1
View
project.name
0 Stars     7 Views
User:
User Image veeresh

Untitled

Untitled
1
View

experiment 2

project.name
0 Stars     14 Views
User:
User Image sterie mioara

Lab1 sterie mioara

Lab1 sterie mioara
lab 1
View
project.name
0 Stars     31 Views
User:
User Image Rafael Sang-Yum

Basic Gates

Basic Gates
Basic Gates Learning 1
View
project.name
0 Stars     9 Views
User:
User Image Gnana PrasannaV

8*1

8*1
1
View
project.name
0 Stars     13 Views
User:
User Image Thanushree H J

EXPERIMENT:2

EXPERIMENT:2
1
View
project.name
0 Stars     14 Views
User:
User Image Thanushree H J

Untitled

Untitled
1
View
project.name
1 Stars     12 Views
User:
User Image Thanushree H J

HALF ADDER AND HALF SUBTRACTOR

HALF ADDER AND HALF SUBTRACTOR
1
View
project.name
0 Stars     8 Views
User:
User Image 小宇

Untitled

Untitled
1
View
project.name
0 Stars     10 Views
User:
User Image CHEA KIMHORN

k

k
1
View
project.name
0 Stars     10 Views
User:
User Image Pupaza

Untitled

Untitled
1
View

O recapitulare la lab 4

project.name
0 Stars     9 Views
User:
User Image Dulitha Weerasinghe

1

1
1
View

project

project.name
0 Stars     6 Views
User:
User Image Dulitha Weerasinghe

1

1
1
View

project

project.name
0 Stars     9 Views
User:
User Image Sebastián González Del Moral

Actividad2.A01786196

Actividad2.A01786196
proyect 1
View

Actividad 2: A01786196

project.name
0 Stars     7 Views
User:
User Image honman mak

3X8 decoders

3X8 decoders
1
View
project.name
0 Stars     7 Views
User:
User Image vaflyz

Untitled

Untitled
1
View
project.name
0 Stars     6 Views
User:
User Image Axiel David Raul Yancachajlla Rinza

AXIEL C3 COMPARADOR

AXIEL C3 COMPARADOR
1
View
project.name
0 Stars     6 Views
User:
User Image Not RMT

Untitled

Untitled
1
View
project.name
0 Stars     15 Views
User:
User Image zahraa

digital

digital
1
View
project.name
0 Stars     6 Views
User:
User Image ZEMMM

Untitled1

Untitled1
1
View
project.name
0 Stars     7 Views
User:
User Image lh

123

123
1
View
project.name
0 Stars     6 Views
User:
User Image Mukhlis

pertama

pertama
1
View
project.name
0 Stars     11 Views
User:
User Image Eng_Aakash

HALF SUB

HALF SUB
1
View
project.name
0 Stars     7 Views
User:
User Image PETNIKORN SUVANKAW

1

1
1
View
project.name
0 Stars     7 Views
User:
User Image Avinash Raj

DLD Q2

DLD Q2
Design of a sequential circuit for counting a sequence 0 1 2 4 5 and 6
View
project.name
0 Stars     10 Views
User:
User Image Anurag

lvl 2

lvl 2
1
View
project.name
0 Stars     4 Views
User:
User Image Nicolas Ignacio

1

1
1
View
project.name
0 Stars     6 Views
User:
User Image jafet

tarea2pro2.1

tarea2pro2.1
tarea2 pro2 1
View
project.name
0 Stars     8 Views
User:
User Image Chinmai A

PROJECT-1

PROJECT-1
1
View

ECE2007_P

project.name
0 Stars     5 Views
User:
User Image SUMIT DHAKA

EXP.1

EXP.1
1
View

ALL GATES

project.name
0 Stars     6 Views
User:
User Image anotony kenson

verification of logic gates 1(antony kenson)

verification of logic gates 1(antony kenson)
1
View
project.name
0 Stars     4 Views
User:
User Image Avneesh kumar tripathi

gates

gates
1
View


project.name
0 Stars     4 Views
User:
User Image anotony kenson

verification of boolean laws 1

verification of boolean laws 1
1
View
project.name
0 Stars     5 Views
User:
User Image ASHWIN

HALF ADDER CIRCUIT

HALF ADDER CIRCUIT
1
View

HALF ADDER CIRCUIT:

It is a basic building block of a full adder and other circuits.It consists of two important parts as outputs sum and carry.it is a method of binary addition which consits if X-or gate and AND gate.The combination of two outputs is called the half adder circuit.

Sum-It is the Least Significant Bit 

Carry-It is the Most Significant Bit

It need two K-maps




project.name
0 Stars     6 Views
User:
User Image Mohammed Azeemulla Khan

Annulment Law

Annulment Law
1
View
project.name
0 Stars     9 Views
User:
User Image Kalpana C Rathod

kalpana ECE LAB

kalpana ECE LAB
Logic gates 1
View
project.name
0 Stars     5 Views
User:
User Image shrutika

exp 2

exp 2
EXPT 1
View
project.name
0 Stars     5 Views
User:
User Image Prasad Kalas

VERIFICATION OF LOGIC GATES

VERIFICATION OF LOGIC GATES
1
View
project.name
0 Stars     7 Views
User:
User Image MINJAE KANG

1

1
1
View
project.name
0 Stars     6 Views
User:
User Image himanshu gupta

3*8 decoder

3*8 decoder
1
View
project.name
0 Stars     5 Views
User:
User Image BHASKARG

BHASKAR

BHASKAR
1
View
project.name
0 Stars     4 Views
User:
User Image Jonás

jonas

jonas
1
View
project.name
0 Stars     6 Views
User:
User Image Krishik.R

PROJECT 1

PROJECT 1
1
View
project.name
0 Stars     1 Views
User:
User Image Devang samor

flip flop

flip flop
lab1 1
View
project.name
0 Stars     6 Views
User:
User Image prajwal reddy

PRAJWAL REDDY

PRAJWAL REDDY
1
View
project.name
0 Stars     10 Views
User:
User Image Thodoris Botsolos

chapter1

chapter1
1
View
project.name
0 Stars     6 Views
User:
User Image Lian Vince Cunanan

Logic

Logic
1
View

4bit full subtractor

project.name
0 Stars     3 Views
User:
User Image patss

LDDCC

LDDCC
1
View
project.name
0 Stars     6 Views
User:
User Image Artem potridenniy2

ДЕШЕФРАТОР

ДЕШЕФРАТОР
ДЕШЕФРАТОР 1 2 3 4 битный
View

Дешефрирует двоичные числа в десятичные от 1 до 4. Левая лампа 1. Правая лампа 4.

project.name
0 Stars     5 Views
User:
User Image Daniel Sinaga

123

123
1
View
project.name
0 Stars     4 Views
User:
User Image Lorin

AND Gatter

AND Gatter
1
View

Follow us on:

Facebook Logo Twitter Logo Linkedin Logo Youtube Logo Github Logo
Simulator
Learn
Blog
Examples
Log in
Documentation
Contribute
Teachers
About
Api
FAQ
Incubated From:

Copyright © 2024 CircuitVerse, All rights reserved.