Searched Projects

Tags: 10

project.name
0 Stars     70 Views
User:
User Image 蕭丞佑

101

101
10
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project.name
0 Stars     65 Views
User:
User Image Gayathri S

or gate

or gate
00 01 10 11
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project.name
0 Stars     54 Views
User:
User Image Gayathri S

OR GATE

OR GATE
00 01 10 11
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project.name
0 Stars     58 Views
User:
User Image Gayathri S

nand gate

nand gate
00 01 10 11
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project.name
0 Stars     65 Views
User:
User Image Mandar Uday Patil

verfiy J-K flip flop and implement master Slave condition using JK Flip Flop

verfiy J-K flip flop and implement master Slave condition using JK Flip Flop
L A B 10
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project.name
0 Stars     71 Views
User:
User Image Arif Santoso

Latihan dan presensi 10 Juni 2021

Latihan dan presensi 10 Juni 2021
10 06 2021
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Arif Santoso

19524101

A

project.name
0 Stars     74 Views
User:
User Image Vidhi

41_Vidhi_Full Subtractor

41_Vidhi_Full Subtractor
10
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project.name
0 Stars     37 Views
User:
User Image Vidhi

41_Vidhi_4:1 Multiplexer

41_Vidhi_4:1 Multiplexer
10
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project.name
0 Stars     38 Views
User:
User Image Chirag

21UCS051_Exp9

21UCS051_Exp9
10
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project.name
0 Stars     21 Views
User:
User Image Rakshitha

level 2 half subtractor using nand gate only

level 2 half subtractor using nand gate only
10
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level 2 half subtractor

project.name
0 Stars     29 Views
User:
User Image Pérez Samuel

Untitled

Untitled
F(w x y z) = Σ(8 10 12 13 14).
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project.name
0 Stars     45 Views
User:
User Image Gustavo Ortiz

Mapas K (5 bits)

Mapas K (5 bits)
F(ABCDE)={18 29 5 31 10 21 14 3 7 26 16 1 9 23 28 12 6 0 20 17 30 11 25 4 19}
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