latch

DFF_sim

Full Adder from subcircuit

logic test 1

D-latch

Synch_Div3_Reset

AND

divide by10

Full Adder from subcircuit

ASSIGNMENT 7 SEGMENT

Untitled

D latch with reset and D flip flop with reset and enable

7seg-input

1

logic test 1

test

Asynch_Synch_Div4

and

Latch_0331

latch+7-seg

gated SR-latch

Untitled

Latch_sim

DFF_Div_2

Dlatch

7 Segment Display

ALU-74LS181

DFF_counter

Encoder, Decoder, and 7-Segment Controller

ALU-74LS181

BCD counter