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latch
latchEncoder, Decoder, and 7-Segment Controller
Encoder, Decoder, and 7-Segment ControllerDFF_sim
DFF_simFull Adder from subcircuit
Full Adder from subcircuitlogic test 1
logic test 1D-latch
D-latchSynch_Div3_Reset
Synch_Div3_Reset7seg-input
7seg-inputAND
ANDdivide by10
divide by10Full Adder from subcircuit
Full Adder from subcircuitASSIGNMENT 7 SEGMENT
ASSIGNMENT 7 SEGMENTBCD counter
BCD counterUntitled
UntitledD latch with reset and D flip flop with reset and enable
D latch with reset and D flip flop with reset and enable1
1logic test 1
logic test 1ALU-74LS181
ALU-74LS181test
testand
andLatch_0331
Latch_0331latch+7-seg
latch+7-seggated SR-latch
gated SR-latchUntitled
UntitledLatch_sim
Latch_simDFF_Div_2
DFF_Div_2Dlatch
DlatchAsynch_Synch_Div4
Asynch_Synch_Div47 Segment Display
7 Segment DisplayDFF_counter
DFF_counterALU-74LS181
ALU-74LS181