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latch
latchDFF_sim
DFF_simFull Adder from subcircuit
Full Adder from subcircuitlogic test 1
logic test 1D-latch
D-latchSynch_Div3_Reset
Synch_Div3_ResetAND
ANDdivide by10
divide by10Full Adder from subcircuit
Full Adder from subcircuitASSIGNMENT 7 SEGMENT
ASSIGNMENT 7 SEGMENTUntitled
UntitledD latch with reset and D flip flop with reset and enable
D latch with reset and D flip flop with reset and enable7seg-input
7seg-input1
1logic test 1
logic test 1test
testAsynch_Synch_Div4
Asynch_Synch_Div4and
andLatch_0331
Latch_0331latch+7-seg
latch+7-seggated SR-latch
gated SR-latchUntitled
UntitledLatch_sim
Latch_simDFF_Div_2
DFF_Div_2Dlatch
Dlatch7 Segment Display
7 Segment DisplayALU-74LS181
ALU-74LS181DFF_counter
DFF_counterEncoder, Decoder, and 7-Segment Controller
Encoder, Decoder, and 7-Segment ControllerALU-74LS181
ALU-74LS181BCD counter
BCD counter