project.name

Vidhi

Member since: 266 days

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41_Vidhi_Logic Gates(OR)

41_Vidhi_Logic Gates(OR)
Public
41_Vidhi_Logic Gates(OR)

41_Vidhi_Logic Gates_(NOT)

41_Vidhi_Logic Gates_(NOT)
Public
41_Vidhi_Logic Gates_(NOT)

41_Vidhi_Logic Gates_(XOR)

41_Vidhi_Logic Gates_(XOR)
Public
41_Vidhi_Logic Gates_(XOR)

41_Vidhi_Half Adder

41_Vidhi_Half Adder
Public
41_Vidhi_Half Adder

41_Vidhi_4:1 Multiplexer

41_Vidhi_4:1 Multiplexer
Public
41_Vidhi_4:1 Multiplexer

41_Vidhi_4:2 Priority Encoder

41_Vidhi_4:2 Priority Encoder
Public
41_Vidhi_4:2 Priority Encoder

41_Vidhi_4 bit binary parallel adder

41_Vidhi_4 bit binary parallel adder
Public
41_Vidhi_4 bit binary parallel adder

41_Vidhi_Full Adder

41_Vidhi_Full Adder
Public
41_Vidhi_Full Adder

41_Vidhi_Logic Gates_(XNOR)

41_Vidhi_Logic Gates_(XNOR)
Public
41_Vidhi_Logic Gates_(XNOR)

41_Vidhi_Logic gates(NOR)

41_Vidhi_Logic gates(NOR)
Public
41_Vidhi_Logic gates(NOR)

41_Vidhi Prajapati_Logic Gates (AND)

41_Vidhi Prajapati_Logic Gates (AND)
Public
41_Vidhi Prajapati_Logic Gates (AND)

41_Vidhi_Half Subtractor

41_Vidhi_Half Subtractor
Public
41_Vidhi_Half Subtractor

41_Vidhi_BCD to Decimal encoder

41_Vidhi_BCD to Decimal encoder
Public
41_Vidhi_BCD to Decimal encoder

41_Vidhi_Full Subtractor

41_Vidhi_Full Subtractor
Public
41_Vidhi_Full Subtractor

41_Vidhi_Logic Gates_(NAND)

41_Vidhi_Logic Gates_(NAND)
Public
41_Vidhi_Logic Gates_(NAND)
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