I have a simple circuit using some latches and tri-state drivers.
On one clock, I get a stack overflow message but it is not obvious why.
The fault occurs when the WR input is manually toggled from 0 to 1.
The Verilog text is here:
/**
* This is an autogenerated netlist code from CircuitVerse. Verilog Code can be
* tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. Thi...
Created by Kurt Zierhut• 2 years ago
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